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VHDL by VHDLwhiz

VHDLwhiz.com

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13,937 installs
| (2) | Free
Snippets, templates, syntax highlighting and code completion
Installation
Launch VS Code Quick Open (Ctrl+P), paste the following command, and press enter.
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VHDL by VHDLwhiz

VHDL support for Visual Studio Code

VHDL by VHDLwhiz is a fork of the puorc.awesome-vhdl plugin with altered snippets that conform to the VHDLwhiz coding style. It includes templates for VHDL modules, testbenches, and ModelSim DO scripts.

I've forked my favorite VHDL plugin to make it better. Save time by using this plugin to generate the initial project files for you!

What's new in version 1.2.15 (January 27, 2022)

  • Added syntax highlighting for "context" keyword

What's new in version 1.2.14 (November 29, 2021)

  • Fixed snippet list on the Details page not rendering correctly

What's new in version 1.2.13 (November 25, 2021)

  • Added "-voptargs=+acc" to modelsimrundo snippet to prevent Questa from removing unused signals
  • New "sh" snippet for creating a shared variable
  • New "ox" snippet for (others => 'X')
  • Changed "pro" snippet with option to delete sensitivity list after first Tab
  • Changed range of std_logic_vector in "typarr" snippet to "downto"
  • Minor improvements to other snippets

Demo video

Demo of the VHDL by VHDLwhiz VSCode plugin

Features

  • Syntax highlighting
  • Code snippets
  • Code completion
  • Brace matching
  • Line and block commenting

DO script (Tcl) snippets

Snippet Description
modelsimrundo Generate a run.do script for a VHDL testbench

VHDL snippets

When you type a snippet in a VHDL file and hit Enter, the plugin will generate template code for you. Then, use the Tab key to move the cursor to the next placeholder.

SnippetDescription
asassert default severity
aswassert warning
aseassert error
asfassert failure
archarchitecture
cconstant
cacase
decrsig <= sig - 1
elelse
elielsif
ententity
entarchentity architecture
fafalling_edge()
fofor loop
funfunction
genfor generate
iif else
incrsig <= sig + 1
intinteger
intdinteger range x downto y
inttinteger range x to y
o0others => '0')
o1others => '1')
oxothers => 'X')
packpackage
proprocess
proarasynch process with reset
profsmFSM process
prossynch process
prosrsynch process with reset
procprocedure
repreport a message
rirising_edge()
ssignal
shshared variable
sisigned
sidsigned(x downto y)
sitsigned(x to y)
sirsigned(sig'range)
slstd_logic
slvstd_logic_vector
slvdstd_logic_vector(x downto y)
slvtstd_logic_vector(x to y)
slvrstd_logic_vector(sig'range)
toito_integer(sig)
tosto_signed(-1, sig'length)
touto_unsigned(0, sig'length)
typarrarray type
typfsmFSM type/signal
typrecrecord type
ununsigned
undunsigned(x downto y)
untunsigned(x to y)
unrunsigned(sig'range)
vvariable
vhdlVHDL template
vhdltbVHDL testbench template
wwhen STATE =>
whwhile loop
wfwait for
wowait on
wuwait until

Installation

Install from the Visual Studio Marketplace or by searching for "vhdlwhiz.vhdl-by-vhdlwhiz" in the Extension view (Ctrl+Shift+X) in VSCode.

License

This extension is licensed under the MIT License. Please see the third-party notices file for details on the third-party binaries that we include with releases of this project.

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