Index

Introduction
Thanks
Go to definition
Hover and structure
Template generator
Documenter
Errors checking
Style checking
Formatting
State machine viewer
State machine designer
Dependencies viewer
Hover to evaluate binary, hexadecimal and octal values
Code snippets and grammar
Beta Verilog/SV schematic viewer
Project manager (currently only VUnit supported
Future work
Similar projects

1. Introduction

Our philosophy is: think in hardware, develop hardware, take advantage of software tools.

The goal of TerosHDL is make the FPGA development easier and reliable. It is a powerful open source IDE.

Please, visit the documentation web for a full IDE description: (https://terostechnology.github.io/terosHDLdoc/)

2. Thanks

Verilog HDL/SystemVerilog (https://marketplace.visualstudio.com/items?itemName=mshr-h.VerilogHDL)
VUnit (https://vunit.github.io/)
VSG (https://github.com/jeremiah-c-leary/vhdl-style-guide)
Wavedrom (https://github.com/wavedrom/wavedrom)
VHDL formatter (https://github.com/g2384/VHDLFormatter)
Yosys (http://www.clifford.at/yosys/)
Tree-sitter-VHDL (https://github.com/alemuller/tree-sitter-vhdl)
Tree-sitter-Verilog (https://github.com/tree-sitter/tree-sitter-verilog)

3. Go to definition

You can jump to the definition with Ctrl+Click.

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4. Hover and structure

If you hover over a symbol, a preview of the declaration will appear.

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5. Template generator

Supported templates

Verilog	VHDL
Testbench	Testbench
cocotb	cocotb
VUnit	VUnit
Signals	Signals
Component	Component
Instance	Instance
Verilator

Usage Instructions

Open a VHDL/Verilog file.
Select the template icon.
Choose a template type.

6. Documenter

Special comment symbols

You can configure what symbol will be used to extract the comments in the HDL file. It supports MarkDown style. In the following example is used the symbol "!":

--! This is a description
--! of the entity.
entity counter is
  port (
    clk: in std_logic; --! Clock comment
    out_data: out std_logic --! Description **port comment**
  );
end counter;

Usage Instructions

Open a VHDL/Verilog file.
Select the documenter icon.
TerosHDL will show the generated documentation.
Export your documentation to PDF, Markdown, HTML or SVG diagram.
Edit your VHDL/Verilog file and save it. The preview will show automatically.

Wavedrom support

TerosHDL supports WaveJSON format in the module description, a format that describes Digital Timing Diagrams:

https://wavedrom.com/tutorial.html

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Bitfield

https://observablehq.com/collection/@drom/bitfield

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7. Errors checking

Supported linters

You need to install manually the simulators.

Verilog	VHDL
ModelSim	ModelSim
Vivado	Vivado
Icarus	GHDL
Verilator

Configuration

One of the above tools has to be installed to enable linter functionalities in a language. If the tool can not be find in the system path it has to be configured in the plugin config:

Configuration example for verilog:

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8. Style checking

Supported linters

This is an experimental feature. You need to install Verible (https://github.com/google/verible)

Verilog	VHDL
Verible	--

Configuration

9. Formatting

Supported formatters

Verilog	VHDL
iStyle	Standalone

Configuration

10. State machine viewer

Usage Instructions

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11. State machine designer

Usage Instructions

Open the command palette: Ctrl+Shift+P and select State machine designer
Follow the instructions and design your state machine!

12. Dependencies viewer

Install Python3.
Go go TerosHDL configuration and add the Python3 binary path.

Usage Instructions

Open the command palette: Ctrl+Shift+P and select Open dependencies viewer
Add a HDL files to the viewer (you can mix verilog and VHDL).
TerosHDL will generate the dependencies graph:
You can reset your viewer:
You can generate the indexed Markdown documentation for all the files.
And the indexed HTML documentation.
Result in HTML format: