Index
1. IntroductionOur philosophy is: think in hardware, develop hardware, take advantage of software tools. The goal of TerosHDL is make the FPGA development easier and reliable. It is a powerful open source IDE. Please, visit the documentation web for a full IDE description: (https://terostechnology.github.io/terosHDLdoc/) 2. Thanks
3. Go to definitionYou can jump to the definition with Ctrl+Click. 4. Hover and structureIf you hover over a symbol, a preview of the declaration will appear. 5. Template generatorSupported templates
Usage Instructions
6. DocumenterSpecial comment symbolsYou can configure what symbol will be used to extract the comments in the HDL file. It supports MarkDown style. In the following example is used the symbol "!":
Usage Instructions
Wavedrom supportTerosHDL supports WaveJSON format in the module description, a format that describes Digital Timing Diagrams: https://wavedrom.com/tutorial.html Bitfieldhttps://observablehq.com/collection/@drom/bitfield 7. Errors checkingSupported lintersYou need to install manually the simulators.
ConfigurationOne of the above tools has to be installed to enable linter functionalities in a language. If the tool can not be find in the system path it has to be configured in the plugin config: Configuration example for verilog: 8. Style checkingSupported lintersThis is an experimental feature. You need to install Verible (https://github.com/google/verible)
Configuration9. FormattingSupported formatters
Configuration10. State machine viewerUsage Instructions11. State machine designerUsage Instructions
12. Dependencies viewer
Usage Instructions
13. Hover to evaluate binary, hexadecimal and octal values14. Code snippets and grammar
15. Beta Verilog/SV schematic viewer16. Project manager (currently only VUnit supported)For a full description visit the documentation web. 17. Future work
18. Similar projects |