SystemVerilog Pro

Lightweight, blazing-fast SystemVerilog, Verilog & UVM extension for VS Code

🚀 Why SystemVerilog Pro?

Built for real-world projects. Unlike other extensions that slow down on large codebases, SystemVerilog Pro is optimized for massive projects (10GB+) with instant response times.

⚡ Instant — No background indexing, no lag
🧠 Smart — Context-aware completions with symbol caching
🎯 Focused — Essential features that just work
🔋 Lightweight — Minimal memory footprint

✨ Features

📝 Intelligent Code Completion

SystemVerilog Keywords & Constructs

module, class, function, task, always_ff, always_comb, 
constraint, covergroup, assertion, and 100+ more...

System Tasks — Type $ to trigger

$display, $finish, $random, $bits, $clog2, $sformatf...

Preprocessor Directives — Type ` to trigger

`include, `define, `ifdef, `ifndef, `endif, `timescale...

UVM Macros — With smart snippets

`uvm_info, `uvm_error, `uvm_component_utils, `uvm_do_with...

UVM Classes & Phases

uvm_component, uvm_driver, uvm_sequence, build_phase, run_phase...

🔄 Smart Symbol Caching

Symbols from files you've opened are cached and available for autocomplete:

Source	Priority	Behavior
Current file	Highest	Always scanned
Open tabs	High	Real-time updates
Previously opened	Medium	Cached for session

Result: Open a file once, and its classes, functions, and types are available everywhere!

🔢 Numeric Hover — Unique Feature!

Hover over any number to see instant conversions:

Hover on...	Shows...
`8'hFF`	Decimal: 255, Binary: 0b11111111
`32'b1010_0101`	Decimal: 165, Hex: 0xA5
`16'd1024`	Hex: 0x400, Binary: 0b...
`8'shFF`	Signed: -1, Unsigned: 255
`[31:0]`	Width: 32 bits, Bytes: 4

🎨 Syntax Highlighting

Comprehensive TextMate grammar covering:

Modules, Classes, Interfaces, Packages
Tasks, Functions, Constraints
Assertions, Coverage, Properties
UVM constructs and macros

🌈 Semantic Highlighting

Visual distinction for ports and parameters:

Input ports — Teal
Output ports — Coral
Inout ports — Purple
Parameters — Gold, italic

📑 Document Outline

Navigate your code with the Outline view:

Modules, Classes, Interfaces
Functions, Tasks
Packages, Programs

🔗 Block Pair Matching

Click on any block keyword to highlight its pair:

begin ↔ end
module ↔ endmodule
class ↔ endclass
function ↔ endfunction
fork ↔ join / join_any / join_none
And 15+ more pairs...

📏 Code Formatting

Auto-indent your code with Shift+Alt+F:

Consistent block indentation
Proper nesting levels

📦 Installation

From VS Code

Open Extensions (Ctrl+Shift+X)
Search "SystemVerilog Pro"
Click Install

From Command Line

code --install-extension taanaya.systemverilog-pro

🎮 Quick Start

Action	Trigger
Keywords & symbols	Just start typing
System tasks	Type `$`
Preprocessor & UVM macros	Type `
Number info	Hover on any number
Bit width info	Hover on `[31:0]`
Format code	`Shift+Alt+F`
Navigate	Use Outline view
Match blocks	Click on `begin`, `module`, etc.

📁 Supported Files

Extension	Language
`.sv`	SystemVerilog
`.svh`	SystemVerilog Header
`.v`	Verilog
`.vh`	Verilog Header

⚡ Performance

Designed for speed on massive codebases:

Feature	Implementation
Completion	Per-file + cached symbols
Hover	Per-file analysis
Formatting	Per-file processing
Highlighting	Per-file tokens

No workspace scanning. No background indexing. Just instant results.

🛠️ Requirements

VS Code 1.75.0 or higher

📄 License

MIT License — see LICENSE for details.

🤝 Contributing

Found a bug? Have a feature request?

👨‍💻 Author

Taher Anaya

📧 taherAnayaDv@gmail.com
🐙 @TaherAnaya

Made with ❤️ for the hardware design community

_{If you find this extension useful, please consider giving it a ⭐ on the marketplace!}