SystemVerilog Pro

The most complete SystemVerilog, Verilog & UVM extension for VS Code
Go to Definition, Hover, Find References, Signature Help, Autocomplete with segment-aware fuzzy matching, and deep symbol indexing — built for very large-scale projects.

Why SystemVerilog Pro?

Built for real-world verification projects. Other extensions choke on large codebases or require a language server. SystemVerilog Pro indexes the entire workspace in the background with multi-threaded workers and keeps the index fresh automatically.

• Fast — Background indexing with multi-threaded workers; automatic re-indexing when stale
• Deep — Resolves dot-access chains, inheritance, :: scope, and method returns
• Complete — Go to Definition, Hover, Find References, Signature Help, and Autocomplete across all workspace files
• Smart — Segment-aware fuzzy matching finds check_leftover_transactions when you type left_trans
• Resilient — File system watchers detect external changes; auto re-indexes when stale

Features

Go to Definition (Cmd+Click / F12)

Jump directly to the declaration of any symbol across your entire workspace:

• Modules, Classes, Interfaces, Packages — click and jump to file
• Functions & Tasks — including extern and DPI imports
• Typedefs, Structs, Enums — including nested and parameterized types
• Variables — resolves custom-type declarations (my_config cfg;)
• **define Macros** — click a backtick macro to jump to its `` define ``
• include Files — click an include path to open the file
• Dot-access chains — cfg.model.block_i[idx].regs resolves each member through the type chain
• :: Scope resolution — pkg::type, Class::static_method, type_id::create()
• Method return chaining — get_reg().field.get() follows return types
• Inheritance — walks extends and implements chains via BFS

Hover Information

Hover any symbol to see its type, source file, line number, and declaration:

• Variables — shows type and where declared
• Functions/Tasks — shows return type and source
• Classes/Modules — shows parent class and file
• Dot-access members — resolves through full type chain
• Macros — shows the `define source

Find All References (Shift+F12)

Right-click any symbol and find every file and line that references it across the workspace. Uses the in-memory symbol index for instant results.

Signature Help

Type ( after a function or task name to see a tooltip showing parameter names. As you type commas, the active parameter is highlighted. Works for all indexed functions and tasks across the workspace.

Intelligent Autocomplete

Context-aware completions from the entire workspace with advanced matching:

• 100+ SystemVerilog keywords — module, class, always_ff, constraint, etc.
• 40+ System tasks — type $ to trigger ($display, $clog2, $sformatf, ...)
• Preprocessor directives — type ` to trigger (`include, `define, `ifdef, ...)
• UVM macros with snippets — `uvm_info, `uvm_error, `uvm_component_utils, ...
• UVM classes & phases — uvm_component, build_phase, run_phase, ...
• Workspace symbols — every module, class, function, task, typedef, enum, variable, and port from all indexed files
• Dot-member completion — type obj. to see members of the resolved type, with proper icons (function, task, variable, etc.)
• Segment-aware fuzzy matching — type left_trans to find check_leftover_transactions; each underscore-separated segment matches the start of a corresponding segment in symbol names
• Proximity-based sorting — symbols from the current file rank first, then same directory, then nearby directories, then the rest of the workspace
• Substring matching — type any part of a name (e.g., type_string) to find symbols like get_fragment_type_string

Background Symbol Indexing

Indexes all workspace files in the background with multi-threaded workers:

Smart Re-indexing

• Full workspace indexing on startup with multi-threaded workers
• Incremental updates on open, edit, save, create, delete, and rename
• File system watchers detect external disk changes (e.g., git pull) and re-index affected files automatically
• Auto re-index on window focus when the index is older than 2 hours — no manual action needed
• Manual re-index via Command Palette: SystemVerilog Pro: Re-index Workspace
• Status bar shows progress during indexing and hides when complete

Syntax & Semantic Highlighting

TextMate grammar covering all SystemVerilog/Verilog/UVM constructs.

Semantic highlighting for ports and parameters:

• Input ports — Teal
• Output ports — Coral
• Inout ports — Purple
• Parameters — Gold, italic

Block Pair Matching

Click on any block keyword to highlight its pair (comment/string-aware):

• begin / end, module / endmodule, class / endclass
• function / endfunction, task / endtask
• fork / join / join_any / join_none
• And 15+ more pairs...

Document Outline

Navigate your code with the Outline view:

• Modules, Classes, Interfaces, Packages
• Functions, Tasks, Programs

Code Formatting

Auto-indent with Shift+Alt+F — consistent block indentation.

Supported Files

Quick Start

Performance

Designed for massive codebases:

Requirements

• VS Code 1.85.0 or higher

License

MIT License

Author

Taher Anaya

• taherAnayaDv@gmail.com
• @anayaTaher

Made with care for the hardware verification community

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