HDL Checker can infer the compilation sequence even without a project file. This sequence can also be inspected by hovering over the name of a design unit
Inferred libraries and files can be inspected by hovering over their instantiation
HDL Checker is a language server that wraps VHDL/Verilg/SystemVerilog
compilers/tools that aims to reduce the boilerplate code needed to set things up.
It supports Language Server Protocol or a custom HTTP interface; can infer
library VHDL files likely belong to, besides working out mixed language
dependencies, compilation order, interpreting some compilers messages and
providing some (limited) static checks.