TL-Verilog support for VSCode
TL-Verilog support inspired by SystemVerilog extension.
How to use
- Install
TL-Verilog extension (eq. search "tlv" in extensions tab)
- Reload VSCode (it will prompt you)
- Open .tlv file
- Enjoy
Features
Done
- Syntax highlighting for
.tlv .TLV files
Known bugs
- None so far
- Open the issue in one of the repos
Git repos
Repository organization
This repository is organized as follows:
sytnaxes/ syntax definition
snippets/ code snippet
src/ source code for custom feature
language-configuration.json language configuration
package.json package configuration
LICENSE.txt license
README.md readme
Contributing
- Fork it ( rweda/tlv-vscode )
- Create your feature branch (
git checkout -b my-new-feature)
- Commit your changes (
git commit -am 'Add some feature')
- Push to the branch (
git push origin my-new-feature)
- Create a new Pull Request
See also
TL-Verilog
License
MIT
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