WaveRenderSVA Enhanced - WaveDrom to SystemVerilog Assertion Generator

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A VS Code extension that renders waveforms with WaveDrom and automatically generates SystemVerilog Assertions (SVA) from JSON waveform descriptions for hardware verification.

What This Extension Does

WaveRenderSVA Enhanced is a VS Code extension that automatically generates SystemVerilog Assertions from WaveDrom JSON files.

Key Features

• WaveDrom Timing Diagram Display - Generate visual waveform diagrams from JSON
• Automatic SystemVerilog Assertion Generation - Create SVA properties from timing relationships
• Assertion File Export - Save generated SVA as .sv files
• Precise Timing Calculation - Generate accurate delay constraints from node positions
• Rich Operator Support - Support for spline(~>), sharp(-|>), immediate(->) and more

Sample Input and Generated Assertions

Example 1: Basic Timing Relationships

Input: WaveDrom JSON

{
  "signal": [
    { "name": "req",   "wave": "01..0.", "node": ".a..b." },
    { "name": "ack",   "wave": "0.1.0.", "node": "..c.d." },
    { "name": "data",  "wave": "x.==.x", "node": "..e.f." }
  ],
  "edge": [
    "a~>c", "c->e", "b-|>d"
  ]
}

Output: Generated SystemVerilog Assertions

// SystemVerilog Assertions generated from WaveDrom
// Generator: WaveformToSVAGenerator v2.0 (Enhanced)

// Flexible connection: a~>c
property edge_a_to_c_0;
  @(posedge clk) disable iff (!rst_n)
  $rose(req) |=> ##[0:1] $rose(ack);
endproperty

// Immediate connection: c->e  
property edge_c_to_e_1;
  @(posedge clk) disable iff (!rst_n)
  $rose(ack) |-> $changed(data);
endproperty

// Strict direction: b-|>d
property edge_b_to_d_2;
  @(posedge clk) disable iff (!rst_n)
  $fell(req) |-> $fell(ack);
endproperty

Example 2: Flexible Timing

Input: Variable Delay Tolerance

{
  "signal": [
    { "name": "req", "wave": "01......", "node": ".a......" },
    { "name": "gnt", "wave": "0..1....", "node": "...b...." },
    { "name": "data", "wave": "x....=..", "node": ".....c.." },
    { "name": "ack", "wave": "0......1", "node": ".......d" }
  ],
  "edge": ["a~>b", "b~>c", "a~>d"]
}

Output: Flexible Timing Constraints

// Request to grant (flexible 0-2 cycles)
property edge_a_to_b_0;
  @(posedge clk) disable iff (!rst_n)
  $rose(req) |=> ##[0:2] $rose(gnt);
endproperty

// Grant to data (flexible 0-2 cycles)
property edge_b_to_c_1;
  @(posedge clk) disable iff (!rst_n)
  $rose(gnt) |=> ##[0:2] $changed(data);
endproperty

// Request to ack (flexible 0-6 cycles)
property edge_a_to_d_2;
  @(posedge clk) disable iff (!rst_n)
  $rose(req) |=> ##[0:6] $rose(ack);
endproperty

Example 3: Immediate Timing

Input: Same-Cycle Relationships

{
  "signal": [
    { "name": "enable", "wave": "01.0....", "node": ".a.b...." },
    { "name": "ready",  "wave": "01.0....", "node": ".c.d...." },
    { "name": "valid",  "wave": "0.10....", "node": "..ef...." },
    { "name": "start",  "wave": "0..1.0..", "node": "...gh..." }
  ],
  "edge": ["a->c", "c->e", "f->g", "g->h"]
}

Output: Immediate Response Assertions

// Enable to ready (same cycle)
property edge_a_to_c_0;
  @(posedge clk) disable iff (!rst_n)
  $rose(enable) |-> $rose(ready);
endproperty

// Ready to valid (next cycle)
property edge_c_to_e_1;
  @(posedge clk) disable iff (!rst_n)
  $rose(ready) |=> ##1 $rose(valid);
endproperty

// Valid fall to start rise (same cycle)
property edge_f_to_g_2;
  @(posedge clk) disable iff (!rst_n)
  $fell(valid) |-> $rose(start);
endproperty

Example 4: Exact Timing

Input: Fixed Delay Requirements

{
  "signal": [
    { "name": "trigger", "wave": "01.....", "node": ".a....." },
    { "name": "response", "wave": "0...1..", "node": "....b.." },
    { "name": "timeout", "wave": "0.....1", "node": "......c" }
  ],
  "edge": ["a-|>b", "a-|>c"]
}

Output: Exact Timing Assertions

// Trigger to response (exactly 3 cycles)
property edge_a_to_b_0;
  @(posedge clk) disable iff (!rst_n)
  $rose(trigger) |=> ##3 $rose(response);
endproperty

// Trigger to timeout (exactly 5 cycles)
property edge_a_to_c_1;
  @(posedge clk) disable iff (!rst_n)
  $rose(trigger) |=> ##5 $rose(timeout);
endproperty

Screenshots

1. WaveDrom Rendering and Live Editing

2. SystemVerilog Assertion Generation

3. Generated Assertion File

How to Use

1. Installation

Install "WaveRenderSVA Enhanced" from VS Code Marketplace

2. Open WaveDrom JSON File

{
  "signal": [
    { "name": "clk",    "wave": "p......." },
    { "name": "enable", "wave": "01....0.", "node": ".a....b." },
    { "name": "data",   "wave": "x.===.x.", "node": "..c.d.e." }
  ],
  "edge": ["a~>c", "c->d"]
}

3. Execute Commands

Ctrl+Shift+P → Search "WaveDrom"

Available Commands

• WaveDrom: Preview - Display waveform diagram
• WaveDrom: Generate SVA - Generate SystemVerilog Assertions
• WaveDrom: Export SVA - Save as .sv file

4. Operator Usage

5. Advanced Features

Conditional Guards

{
  "signal": [
    { "name": "req", "wave": "01.0", "node": ".a.b" },
    { "name": "ack", "wave": "0.10", "node": "..c." }
  ],
  "edge": ["a~>$|(enable)$c"]
}

Release History

v0.30.1 (2025-09-01) - Issue #3 Implementation

• ✅ Precise Timing Calculation: Accurate delay constraint generation from node positions
• ✅ f~>g → ##[0:1]: Precise timing generation between adjacent nodes
• ✅ Operator Optimization: Optimal pattern generation for each operator characteristic
• ✅ Comprehensive Testing: 42 test cases with 100% success rate

v0.30.0 (2024) - Issue #2 Complete

• <-> Stability Operator: $stable() throughout syntax support
• <~> Change Detection: $changed() with timing constraints
• Conditional Guards: $|(condition)$ and $&(condition)$ support
• IEEE 1800 LRM Compliance: All generated SVA conforms to standard specification

v0.29.0 - Enhanced SVA Generation

• SystemVerilog Assertion automatic generation feature added
• WaveDrom edge syntax support
• Assertion save functionality

v0.28.0 - Core Features

• WaveDrom waveform display functionality
• Live preview mode
• JSON format support

Attribution: This project is a fork and enhancement of waveform-render-vscode by Borja Penuelas (bmpenuelas).

Support: GitHub Issues

Technical Specification: Documentation

Installation

1. Download the .vsix file from GitHub Releases
2. Run code --install-extension waveform-render-sva-enhanced-*.vsix

Development

git clone https://github.com/MameMame777/WaveRenderSVA.git
cd WaveRenderSVA
npm install
npm run compile

Commands

Testing

cd tests
node test_verification.js

Test Results: 42 test cases, 100% success rate with comprehensive Issue #3 timing verification.

License

MIT License - see LICENSE.txt for details.

Version History