Verilog / SystemVerilog Syntax Highlighter (No IntelliSense)

A clean, lightweight, syntax-only extension for Verilog and SystemVerilog created by sohailapril292003.

This extension provides:

• ✔ Syntax highlighting for Verilog (IEEE 1364)
• ✔ Syntax highlighting for SystemVerilog (IEEE 1800)
• ✔ Highlighting for modules, ports, datatypes, operators, and events
• ✔ Highlighting for always/always_ff/always_comb
• ✔ Support for numbers, strings, comments, and system tasks ($display, $time, etc.)
• ✔ Clean grammar structure that allows easy addition of new keywords

❌ No IntelliSense — Pure Syntax Only

This extension intentionally does NOT include:

• No autocomplete
• No suggestions
• No IntelliSense
• No snippets
• No language server
• No hover information

It is built for developers who want a clean Verilog editor with zero distractions, especially useful for learning, academic use, and manual RTL writing.

✨ Features

• Highlight:

  • module / endmodule
  • input, output, inout
  • wire, reg, logic, int, structs
  • always, posedge, negedge
  • assign, deassign, force, release
  • SystemVerilog constructs
  • @, @(*), sensitivity lists
  • operators: ^, &&, ||, shifts, comparisons
  • numeric literals (binary, hex, decimal)

• Future-proof grammar: You can add new keywords anytime inside the grammar file: