SiliCode — VS Code Extension
AI-powered HDL (Verilog/SystemVerilog/VHDL) module generation directly inside VS Code. Connects to the SiliCode Flask backend and provides the same workflow as the web interface.
Requirements
- VS Code 1.74 or later
- SiliCode backend running (Docker recommended) — see parent project
docker/ directory
- Node.js 18+ (for building from source)
Setup
1. Start the backend
From the project root:
cp docker/.env.dev.example docker/.env.dev # first time only — fill in secrets
docker compose -f docker/docker-compose.dev.yml up --build
The API will be available at http://localhost:9090.
2. Build the extension
cd vscode-extension
npm install
npm run compile
3. Run in VS Code
- Open the
vscode-extension/ folder in VS Code.
- Press F5 to launch an Extension Development Host.
- Click the SiliCode circuit-board icon in the Activity Bar.
- Sign in with your backend credentials (default dev:
admin / @dmin123).
4. Rebuild after code changes
If you edited TypeScript (src/):
npm run compile # then reload the Extension Development Host (Ctrl+R)
If you only edited media/ files (HTML/CSS/JS), reloading the dev host window is enough — no recompile needed.
Configuration
| Setting |
Default |
Description |
silicode.apiBaseUrl |
http://localhost:9090 |
Backend base URL. Change for remote or production deployments. |
Set via: File → Preferences → Settings → search "silicode".
Features
Generation Modes
- Agent mode — Direct generation from a natural language hardware description.
- Plan mode — Generates clarifying questions first, refines the spec, then generates.
- PDF files — Attach up to 4 PDF files (max 10 MB each) as context for generation. Uploaded to the RAG service at send time.
- Editor code — Add selected code or the full active file as context (up to 10 snippets). Shown as chips in the message bubble.
Generation Options (Features panel)
| Feature |
Description |
| Search Agent |
Web search to find relevant IP or datasheets |
| Exa Search |
Alternative search engine integration |
| IP Core |
Automatic IP core selection for the target FPGA |
| Code RAG |
Retrieval-augmented code generation from the knowledge base |
| Reflection |
Secondary LLM pass to critique and improve the generated code |
| Auto-Verify |
Run cocotb simulation to verify the generated module |
| Thorough Verify |
Extended verification with more simulation attempts |
IP Core and Code RAG are automatically disabled when VHDL is selected.
Output Languages
Toggle between SV (SystemVerilog) and VHDL using the HDL selector in the input bar.
FPGA Target
Set the synthesis target (Xilinx, Intel, Lattice, Gowin, Generic) inside the Features panel. Affects Yosys synthesis reporting.
Model Selection
Override the generation model per-session using the model selector dropdown. The list is fetched from the backend on first login (cached 1 hour server-side).
Result Cards
Each generated response shows a collapsible card with:
- Module name + status chip (Generated / Passed / simulation failure)
- Module code section (expanded by default)
- Testbench code section (expanded by default)
- Simulation Results section (collapsed — expand to view cocotb output)
- Synthesis section (collapsed — Yosys report with LUT/FF/wire stats and full log)
Synthesis chip colors: green = clean, yellow = warnings, red = error/timeout.
Code Actions
Each code block has four action buttons:
| Button |
Action |
| Copy |
Copy to clipboard |
| Insert |
Insert at cursor in active editor |
| Diff |
Show diff against current editor file (VS Code native diff or inline) |
| Save |
Open Save dialog to write .sv / .v file |
Conversation History
- Click the chat title button or the History icon to open the sidebar.
- Threads are grouped by Today / Yesterday / This Week / Older.
- Follow-up messages continue the same thread — the model remembers context.
- The X button on a thread hides it locally (persisted across VS Code restarts).
Background Generation
If you navigate away (new chat or open history) while a task is running, the server task continues. A pulsing dot in the header indicates a background task. Click the thread in history to resume polling and see results when ready.
VS Code Commands
Available from the Command Palette (Ctrl+Shift+P):
| Command |
Description |
| SiliCode: Open Panel |
Focus the sidebar panel |
| SiliCode: Stop Generation |
Cancel the active task (also available as toolbar button) |
| SiliCode: Show Diff with Generated Code |
Diff editor vs last generated module |
| SiliCode: Insert Module Code to Editor |
Insert last module at cursor |
| SiliCode: Insert Testbench Code to Editor |
Insert last testbench at cursor |
| SiliCode: Save Module to File |
Save last module via dialog |
| SiliCode: Save Testbench to File |
Save last testbench via dialog |
Architecture Notes
- The extension is a zero-background-traffic bridge. It makes no API calls when idle — no connection polling, no pings.
- JWT tokens are stored in VS Code's encrypted secret storage (not plaintext settings).
- All backend communication goes through the extension host (Node.js
http/https). The webview JS has no direct network access.
- Connection loss is detected reactively when a real request fails, not by periodic health checks.
