speja for VS CodeCatch VHDL bugs as you type, not in simulation. speja checks and formats VHDL on every keystroke. Width mismatches, out-of-range indices and
processes that can never suspend are underlined in the editor, long before a testbench would
find them. Switch on more checks, such as latches, multiple drivers and clock-domain crossings,
with one line in Lint and formatNothing else to install: the speja server comes with the extension.
To make speja the VHDL formatter:
Configurespeja reads
On an existing codebase the full VSG rule set can fill the Problems panel; turn off what your project does not follow. Each finding names its rule, and the rule reference lists the options. The bug-finding rules need to know which library each file belongs to. They read the
Editing actions
...and more. speja: Show Actions... (the speja item in the status bar, or right-click) lists the ones that apply where the cursor is. These build on VHDL-LS, so install it alongside. ColourA number of popular Vim colour schemes are available as themes. Learn more
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