VSV — Visualizing SystemVerilog

Real-time block-diagram visualisation for SystemVerilog source files, inside VS Code. Open any .sv file and a side panel renders the module structure as a clean schematic that updates as you type.

Features

VSV cycles between three views with VSV: Toggle Stage (or run VSV: Show Diagram to open the panel):

• Stage 1 – Block view. The module as a single labelled rectangle with every input / output port as a diamond on the boundary.

• Stage 2 – Internal structure. Sub-module instances laid out left-to-right, with wires derived from named port connections and assign-alias resolution. generate-for blocks are expanded into an N-D grid — inner loop left-to-right, outer loop top-to-bottom — so a 4×4 systolic array shows up as a 16-cell grid.

• Stage 3 – RTL synthesis. The behavioural body of a single module is synthesised into primitive shapes:

  Shape	Meaning
  rounded square	arithmetic / logic / comparison / shift operator
  triangle with bubble	logical or bitwise NOT (!, ~)
  vertical trapezoid	2:1 ?: MUX or N:1 case MUX
  rectangle "FF"	edge-triggered flip-flop
  rectangle "latch"	level-sensitive latch
  diamond	module-level input or output

  if/else chains expand to MUX cascades; incomplete always_comb branches trigger an inferred-latch warning in the status bar.

Wire colours follow schematic convention:

• Yellow — module input wire
• Green — module output wire
• Blue — internal wire

Clock and reset signals always enter their target boxes from the top; their source ports float to the upper-left corner of the diagram.

Live updates

The diagram re-renders 300 ms after every keystroke. External changes (git checkout, save from another editor) refresh the active diagram too.

Layout engine

Layout is done by ELKjs with a custom post-processor that pins clk/rst to the upper-left column, rebuilds edge bends as 90° orthogonal routes, and resolves FF feedback cycles so MUXes feeding FF.D always sit to the left of the flip-flop.

Commands

Supported SystemVerilog subset

• Module declarations with #(parameter …) blocks
• ANSI port lists, packed and unpacked array dimensions
• assign, always_ff, always_comb, always_latch, always @(*)
• if / else, case with default
• Sub-module instantiations with named (.port(expr)) port connections
• generate-for blocks (1-D and N-D nested)
• Unsized fill literals ('0, '1, 'x, 'z), sized base literals (8'b…, 16'h…)

Constructs the synthesis view doesn't model — generate blocks, instances, function/task bodies, typedefs — are skipped fail-soft; the diagram still renders everything else.

Known limitations

• Direction of sub-module ports is inferred heuristically when the sub-module isn't visible in the workspace; non-trivial expressions passed to a port may render with the wrong arrow direction.
• always_comb-inferred latches are detected but not yet highlighted inline in the source editor.
• Stage 3 falls back to Stage 2 when a module is purely structural.

Release notes

See CHANGELOG.