This package provides some helpful code generators for using the
Given a verilog module, this will create a snippet for verilog testbench which can be used to bind the module to MyHDL. All nets are initialized as
Given a verilog module, this will create a snippet for that same module in MyHDL format which can be referred to in a MyHDL testbench.
This package relies on Ctags for parsing. The recommended version to install is Universal Ctags
Installation of Universal Ctags
Added Unittest instantiation and updated testbench and bind instantiation.
Added user setting to modify default iverilog myhdl.vpi path.
Added user setting to modify default sources path.
Added functionality for differentiating between input and output ports.
Added file creation functionality.