VIDEVIDE is an extension allowing editing and simulating of a Verilog subset. More details can be found on GitHub: https://github.com/OllyLarkinFYP/FYP/tree/main/front-end/vide. |
VIDEVIDE is an extension allowing editing and simulating of a Verilog subset. More details can be found on GitHub: https://github.com/OllyLarkinFYP/FYP/tree/main/front-end/vide. |