This Visual Studio Code extension provides Syntax Highlighting support for the following languages:
Verilog (.v)
VHDL (.vhd, .vhdl)
SystemVerilog (.sv, .svh)
TCL (.tcl)
TLVerilog (.tlv)
UCF (.ucf)
Features
Syntax Highlighting: Enhanced readability with color-coded syntax for SystemVerilog, Verilog, VHDL, TLVerilog, TCL, and UCF files.
Green Theme: Choose the Green Theme for a visually soothing coding experience. This theme provides a green-based palette, designed to reduce eye strain during long coding sessions. It also helps you quickly identify important elements, spot errors, and find assignments at a glance, allowing you to debug and code efficiently.
Multiple Language Support: Whether you're working on FPGA designs, RTL coding, or configuration files, this extension ensures a consistent and clean syntax highlighting experience across various hardware description and scripting languages.
How to Use
Install the extension from the Visual Studio Code marketplace.
Open any file with the extensions .sv, .svh, .tcl, .tlv, .ucf, .v, .vhd, or .vhdl, and the appropriate syntax highlighting will be applied automatically.
To enable the Green Theme, go to the Visual Studio Code Theme Settings and select Green Theme from the list of available themes.
Enjoy a consistent, visually appealing syntax highlighting experience with full support for hardware description languages and more, all while keeping your workspace green and easy on the eyes!
