General files that will be loaded using the `include statement can be placed in the include/ directory.
(Synthesizable) modules can be placed in the rtl/ directory while modules only required for testing can be seperated in the test/ directory.
The testbench/ directory can contain the required testbenches as well as (optional) waveform display files for Simvision to use.
XCELIUM product suite
Verible Verilog Language Server
This extension contributes the following settings:
iddigital.verible.path: The path to verible-verilog-ls executable, e.g.: /usr/bin/verible-verilog-ls.
iddigital.verible.arguments: Arguments for verible-verilog-ls server.