RTL Viz – RTL Schematics for Verilog/SystemVerilog

See your RTL as you write it. RTL Viz turns Verilog and SystemVerilog into interactive schematics, live next to the editor. Click a signal in code to find it in the graph, click the graph to jump back to source.

Powered by Verilator, bundled as WebAssembly: nothing else to install.

⚡ Quick Start

1. Install RTL Viz from the Extensions view (VS Code Marketplace or Open VSX).
2. (Optional) Install native Verilator for faster runs on large designs, and set rtlviz.verilatorEngine to auto or native.
3. Open a Verilog/SystemVerilog file (.v, .vh, .sv, .svh).
4. Click the RTL Viz: Show Preview button in the editor title bar, or run it from the Command Palette.
5. The RTL graph appears in a side/bottom panel. Clicking in code and graph keeps them in sync.

✨ Features

• Interactive RTL visualization – View your Verilog designs as an RTL schematic generated from Verilator JSON.
• Bidirectional navigation – Click on code to focus the schematic, or click on graph nodes to jump back to source.
• Three‑level highlighting
  • Level 1 (clickable): All elements known to RTL Viz.
  • Level 2 (visible): Elements in the currently rendered cone.
  • Level 3 (selected): The actively selected signal.
• Crystallization point – Focus the graph around a specific signal.
• Per‑folder Verilator options – Configure include paths, filelists, and extra args on a per‑project basis.
• Auto‑refresh – Automatically re‑runs Verilator and updates the schematic on save.
• Auto‑discovery – Missing modules and include files reported by Verilator are located in the workspace and added automatically.
• Hierarchy sidebar – RTL Viz Hierarchy view in the Explorer; expand instances into the schematic.
• Large designs – Streaming JSON parse, chunked transfer, and a per‑instance cone cap (rtlviz.coneRenderLimit) keep big SoCs responsive.

🔧 Requirements

None by default: RTL Viz ships verilator-wasm (Verilator compiled to WebAssembly) and runs it in‑process on any OS. VS Code ≥ 1.90.

Optional native Verilator (5.x) — faster, and required for designs too large for the wasm engine (wasm32 memory limit):

• Install from https://verilator.org/ or your package manager (apt-get install verilator).
• Set rtlviz.verilatorEngine to native (always) or auto (native when found, else wasm).

Verilator must succeed on your design (including all necessary -I and -f flags) with either engine.

🚀 Usage

1. Open a Verilog/SystemVerilog file.
2. Run “RTL Viz: Show Preview” from:
   • The editor title bar button, or
   • The Command Palette (Ctrl+Shift+P).
3. RTL Viz runs Verilator, builds the internal graph, and opens a preview panel.

Interacting with the visualization

• Click in code – Click a variable or signal name in your Verilog code. RTL Viz highlights it and focuses the corresponding node in the graph.
• Click in the graph – Click a node in the schematic to jump to its best matching assignment site (or declaration) in source.
• Zoom the preview – When the preview panel is focused:
  • Ctrl/Cmd + = or Ctrl/Cmd + + to zoom in
  • Ctrl/Cmd + - to zoom out
  • Ctrl/Cmd + 0 to reset zoom to 100%
  • Ctrl/Cmd + Mouse Wheel to zoom with the mouse
  • ℹ️ Webview zoom is independent from VSCode's window zoom
• Highlight levels
  • Light highlight: all clickable elements in the file.
  • Medium highlight: elements visible in the current graph/cone.
  • Strong highlight: the currently selected element.

⚙️ Configuration

This extension contributes the following settings:

• rtlviz.verilatorEngine (string: "wasm" | "native" | "auto")

  • wasm (default): bundled verilator-wasm. native: executable at rtlviz.verilatorPath. auto: native when verilator --version works, else wasm.

• rtlviz.verilatorPath (string)

  • Path to the native Verilator executable (default: "verilator"); used by native / auto.

• rtlviz.verilatorArgs (array of strings)

  • Global extra arguments passed to Verilator.

• rtlviz.verilatorFolderArgs (object)

  • Per‑folder Verilator arguments. Keys are absolute folder paths, values are arrays of args.

  • Example:

    "rtlviz.verilatorFolderArgs": {
      "/path/to/ibex/rtl": [
        "--top-module", "ibex_core",
        "-f/path/to/ibex_verilator_filelist.f"
      ]
    }
    

• rtlviz.folderOptions (object)

  • Per‑folder include directories and filelists maintained by RTL Viz as it discovers missing includes. Normally you do not need to edit this manually.

• rtlviz.autoDiscoverFiles (boolean)

  • Search the workspace for missing modules / include dirs when Verilator reports them (default: true).

• rtlviz.autoRefresh (boolean)

  • Automatically refresh preview on file save (default: true).

• rtlviz.previewLocation (string: "right" | "bottom" | "current")

  • Controls where the preview panel opens relative to the editor.

• rtlviz.pipelineStepTimeoutSeconds (number)

  • Per‑step timeout for the Verilator → render pipeline (default: 120).

• rtlviz.coneRenderLimit (number)

  • Per‑instance cap on rendered cones (default: 5000). Larger instances show a truncation banner; drill down via the hierarchy sidebar.

🩺 Troubleshooting

• Preview is blank

  • Open the “RTL Viz” output channel and check for Verilator errors.
  • Ensure Verilator arguments are correct (and rtlviz.verilatorPath when using the native engine).

• "Design too large for the bundled wasm Verilator"

  • Install native Verilator and set rtlviz.verilatorEngine to native or auto.

• Extension doesn’t seem to activate

  • Open a .v / .sv file first, then run “RTL Viz: Show Preview”.

• Stale discovered files / include dirs

  • Run “RTL Viz: Clear Discovered Files & Include Dirs for Folder”.

💬 Feedback

Questions, bug reports, and feature requests: use the Q & A and Rating & Review tabs on the extension's Marketplace page. When reporting a problem, include the relevant output from the RTL Viz output channel.

📜 License

MIT. The license text ships with the extension (LICENSE).

🙏 Credits

• Built with onml for SVG rendering.
• Uses Verilator for Verilog/SystemVerilog analysis.
• Part of the WaveDrom project family.