Verilog Snippets

This extension for Visual Studio Code adds snippets for Verilog.

Repositories

https://github.com/czh9919/czh-verilog-snippet

Usage

Type a part of keywords in the snippet and press enter. Such as:

parameter
wire
reg
input
output
begin
if
ifelse
elif
else
elseBegin
case
always
always @ case
default
module
assign
generate
localparam