Convoluted

AI-Powered Chip Design

An AI-native development environment for chip design engineers — from RTL to GDSII/OASIS.

Overview

Convoluted is an AI-powered chip design environment built to accelerate the complete digital hardware development workflow.

Inspired by the way AI coding assistants transform software development, Convoluted brings AI assistance directly into the chip-design process.

From writing RTL to running physical design and generating final GDSII/OASIS layouts, Convoluted aims to make the entire workflow faster, more interactive, and easier to iterate.

RTL Development
       │
       ▼
   Synthesis
       │
       ▼
  Floorplanning
       │
       ▼
   Placement
       │
       ▼
     CTS
       │
       ▼
   Routing
       │
       ▼
 Physical Analysis
       │
       ▼
 GDSII / OASIS

The goal is simple:

Reduce the time between a hardware idea and its physical implementation.

Features

AI-Assisted RTL Development

Use AI directly while developing hardware.

Convoluted is designed to assist with:

• Writing RTL
• Modifying existing RTL
• Understanding hardware designs
• Navigating complex RTL projects
• Iterating on hardware implementations
• Accelerating repetitive development tasks

RTL-to-GDSII/OASIS Automation

Convoluted connects RTL development with the downstream physical-design flow.

Instead of manually managing every stage of the process, the environment is designed to automate and coordinate the workflow from RTL through physical implementation to final layout.

┌──────────────┐
│     RTL      │
└──────┬───────┘
       │
       ▼
┌──────────────┐
│  Synthesis   │
└──────┬───────┘
       │
       ▼
┌──────────────┐
│ Floorplanning│
└──────┬───────┘
       │
       ▼
┌──────────────┐
│  Placement   │
└──────┬───────┘
       │
       ▼
┌──────────────┐
│     CTS      │
└──────┬───────┘
       │
       ▼
┌──────────────┐
│   Routing    │
└──────┬───────┘
       │
       ▼
┌──────────────┐
│   Signoff    │
└──────┬───────┘
       │
       ▼
  GDSII / OASIS

Physical Design & P&R

Convoluted brings physical-design workflows closer to the development environment.

The system is designed to assist with:

• Synthesis
• Floorplanning
• Placement
• Clock-tree synthesis
• Routing
• Physical optimization
• Design-flow execution
• Physical-design iteration

This creates a tighter feedback loop between RTL changes and their physical consequences.

Why Convoluted?

Chip design is inherently iterative.

A small RTL change can affect:

• Area
• Timing
• Power
• Placement
• Routing
• Congestion
• Final layout

Traditional workflows often require engineers to manually move between different tools, configurations, logs, scripts, and analysis results.

Convoluted is designed to reduce this overhead.

       Design
          │
          ▼
   AI-assisted change
          │
          ▼
      RTL Flow
          │
          ▼
  Physical Implementation
          │
          ▼
       Analysis
          │
          ▼
        Result
          │
          └──────────► Iterate

The objective is to make this iteration cycle significantly faster.

Built for Chip Design Engineers

Convoluted is built for engineers working on digital hardware and semiconductor design.

It is intended to provide a familiar AI-assisted development experience while operating within the constraints and complexity of real chip-design workflows.

Instead of treating RTL development and physical design as completely separate activities, Convoluted aims to connect them into a single workflow.

AI-Native Hardware Development

Software developers increasingly use AI assistants to write, understand, debug, and modify code.

Convoluted applies the same principle to hardware.

The goal is an AI assistant that can reason across the hardware-development stack:

                Hardware Intent
                       │
                       ▼
                      RTL
                       │
                       ▼
                   Synthesis
                       │
                       ▼
               Physical Design
                       │
                       ▼
                    Analysis
                       │
                       ▼
                 GDSII / OASIS

This allows AI assistance to extend beyond simply generating RTL and into the physical implementation process.

Faster Chip Design Workflows

The primary goal of Convoluted is speed.

Faster:

• RTL development
• Design iteration
• Physical-design execution
• Debugging
• Analysis
• Implementation

By reducing repetitive manual work and connecting the different stages of the design flow, Convoluted aims to shorten the overall development cycle.

Requirements

Convoluted is designed to work with semiconductor design toolchains required for the RTL-to-GDSII/OASIS flow.

The exact requirements depend on the physical-design flow and tools being used.

Supported toolchains and installation requirements will be documented as the project evolves.

Extension Settings

Extension-specific configuration will be documented here as settings are introduced.

Development Status

Convoluted is currently under active development.

The project is being developed toward an AI-assisted environment capable of helping engineers move from RTL development through physical implementation and final GDSII/OASIS generation.

Features and supported workflows may change during development.

Roadmap

RTL Development

• AI-assisted RTL generation
• RTL modification
• RTL understanding
• Hardware architecture assistance
• Intelligent design navigation

Physical Design

• Automated synthesis
• Floorplanning
• Placement
• Clock-tree synthesis
• Routing
• Physical optimization

Analysis

• Timing analysis
• Area analysis
• Power analysis
• Congestion analysis
• Physical-design feedback

Automation

• End-to-end RTL-to-GDSII automation
• RTL-to-OASIS automation
• Automated flow execution
• AI-assisted iteration
• Intelligent error analysis

Vision

The long-term vision of Convoluted is to make chip design more accessible to AI-assisted development.

Instead of engineers spending their time manually operating disconnected tools and managing repetitive flow steps, Convoluted aims to let them focus on the actual hardware.

Describe the hardware. Develop the RTL. Iterate with AI. Build the physical design.

From RTL to GDSII/OASIS, Convoluted is being built to make chip design faster.

License

License information will be added here.