ChipCraftVS: Silicon-Grade RTL, Where You Code

Design hardware in natural language. ChipCraftVS brings synthesis-aware diagnostics, AI-powered RTL generation, and waveform viewing into VS Code, powered by ChipCraftModel-1, a hardware-specialized AI that writes Verilog the way your EDA tools expect it.

Every generation is validated against real EDA toolchains (Icarus Verilog, Verilator, Yosys) before it reaches your editor. No hallucinated syntax, no unsynthesizable constructs.

Your Design Never Leaves Your Infrastructure

ChipCraftVS generates on ChipCraftX infrastructure. Your source code, your specs, and your generated RTL stay on-premise. No public API calls, no third-party model providers, no data leaving your network. This is not a policy toggle: it is the architecture.

For air-gapped and ITAR-sensitive environments, the entire AI pipeline runs against an internal inference endpoint with zero outbound network calls.

Features

Code Intelligence

• Synthesis-aware diagnostics: latch inference, blocking/non-blocking misuse, CDC violations, incomplete sensitivity lists, unsupported constructs
• Cross-file module index: port mismatch detection across instantiations
• Go-to-definition and document/workspace symbols for modules, ports, and signals
• Compile-on-save with iverilog (Verilog-2001) or Verilator (SystemVerilog)
• Standard-aware: .v files enforce Verilog-2001 rules, .sv files enforce SystemVerilog rules

AI Generation with ChipCraftModel-1

• Chat panel: describe a module in plain English, get validated RTL back with visible reasoning steps and iteration progress
• Inline edit (Cmd+K): select code, describe what to change, preview the diff before accepting
• Testbench generation: right-click any module to generate a self-checking testbench
• Hierarchical generation: multi-module designs from a single complex spec
• EDA-validated: every generation passes compile, simulate, and synthesis checks before it is presented to you

Waveform Viewer

• Open .vcd files with a canvas-based signal renderer, dual cursors, zoom and pan
• Simulate and view: compile, simulate, and auto-open the waveform in one command (Ctrl+Shift+W)
• Synthesis dashboard: Yosys results with cell breakdown and LUT/FF counts

Persona System

• 4 personas: Professional, Startup, FPGA, Student
• Passive inference: automatically detects your experience level from editing behavior
• Adaptive AI: prompt style, diagnostic detail, and hover depth adjust per persona
• Educational mode: the Student persona gets step-by-step explanations instead of direct solutions

Getting Started

1. Install ChipCraftVS from the VS Code Marketplace
2. Open a Verilog (.v) or SystemVerilog (.sv) file, and diagnostics activate immediately
3. Run ChipCraftX: Get Started from the command palette to set up AI generation

Commands

Configuration

Requirements

• VS Code 1.85.0 or later
• Optional: iverilog or Verilator (compile-on-save and simulation)
• Optional: Yosys (synthesis dashboard)
• Optional: Python 3.10+ (AI generation features)

License

Copyright 2026 ChipCraftX LLC. All rights reserved.

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