Blueprint RTL

Blueprint RTL automatically generates technical documentation for Verilog/SystemVerilog files and projects.

Features

Describes functionality of modules and projects.
Detects ports, parameters, instances, and state machines, and includes descriptions extracted from comments.
Generates diagrams: module hierarchy and gate-level diagrams.

Right click → Create Documentation
Generate Markdown documentation (.md) from a selected .v/.sv file or folder.
Ctrl+Shift+V → Preview PDF
Open a live PDF preview of the generated Markdown file.
Export
One-click export to PDF, Word (.docx), or Markdown (.md).

Commands

Commands should be put as a comments
- @detailed Put above modules that should not be shown as black box.
  
  Use the command @detailed above an instance.
```
//@detailed
cve2_if_stage if_stage_i (
```
- @highlight_one(name_of_the_signal) Highlights only connection which drives input to the specific module.
  
  Use the command @highlight_one above an instance.
```
//@highlight_one(clk_i)
cve2_if_stage if_stage_i (
  .clk_i (clk_i),
  .rst_ni(rst_ni),
```
- @highlight_all(name_of_the_signal) Highlights all connections of the signal.
  
  Use the command @highlight_all above an instance.
```
//@highlight_all(clk_i)
cve2_if_stage if_stage_i (
  .clk_i (clk_i),
  .rst_ni(rst_ni),
```
- @with_params Include parameters in generated symbol.
  
  Use the command @with_params only above an top module instance.
```
//@with_params
module cve2_counter #(
  parameter int CounterWidth = 32,
  parameter bit ProvideValUpd = 0
) 
```

If you find any bugs or have suggestions for future updates contact us at design@blueprintrtl.com