VS Code DVT IDE for Verilog/SystemVerilog/VHDL
Starting with version 23.2.23 a FlexLM license server ≥11.19 is required.
Requirements: VS Code >= 1.93.1
Commercial License: By downloading and using the DVT IDE for Visual Studio Code, you agree to the product End-User License Agreement.
Design and Verification Tools (DVT) IDE significantly improves productivity for design and verification engineers who are using VS Code with Verilog, SystemVerilog, Verilog-AMS or VHDL.
Unlike plain text editors providing regular expression based capabilities, the DVT IDE compiles the code and signals errors as you type, speeds-up code writing using auto-complete and quick fix proposals, and allows you to find anything you are looking for instantly.
What the DVT IDE for VS Code can give you in seconds would likely have taken you several minutes or hours to find and do by hand.
The DVT IDE enables engineers to overcome the limitations of plain text code editors and address today’s project complexity more efficiently. It allows for faster and smarter code development and simplifies legacy code maintenance for novices and experts alike.
Features
- On the fly standard compliant compilation. The DVT IDE uses an IEEE standard compliant parser (IEEE 1800 SystemVerilog, IEEE 1076 VHDL). There is no need to invoke the simulator to make sure the code compiles without errors. DVT IDE performs on-the-fly incremental compilation and as such, the editor highlights the errors in real time, as you type.
- Advanced code editing capabilities such as autocomplete, quick fixes, macro expansion, intelligent code formatting, refactoring, and code templates.
- Code and project navigation features such as hyperlinks, structural browsing (e.g. design hierarchy), dynamically created UML diagrams and design diagrams. These features enable users to navigate easily through tens of thousands of code lines, locate the relevant information, inspect a class or module structure, and understand the source code quickly.
- Cross-language capabilities for mixed-language projects allows users to work with source code written in multiple languages (i.e. SystemVerilog, Verilog, VHDL), navigate seamlessly through large projects, easily see the big picture, and understand the whole design.
You can also browse the documentation for DVT IDE for VS Code online.
License
By downloading and using the DVT IDE for Visual Studio Code, you agree to the product End-User License Agreement.
Features
Compilation
Quick Fix Proposals
Add Port
Add Parameter / Update Module Instance
Add Signal to Sensitivity List / Remove Signal from Sensitivity List / Remove Signal Never Used
Create Class In New File
Create Interface Class In New File
Import Type
Implement Extern Method / Implement Missing Pure Virtual Methods / Add Virtual Qualifier to Interface Type / Remove 'local' or 'protected' Qualifier
Fully Qualify Type
Create Included File
Create File From Build Config Editor
Did You Mean? / Declare Variable
Declare Method
Update Extern Prototype or Implementation / Update Virtual Method Signature
Add Case Choice / Declare Enum Value
Add Generic to Entity
Replace Deprecated Package
Remove Library Clause
Update Entity Instance
Hyperlinks
Go to Declaration
Go to Definition
Go to Super / Child Implementation
Go to Type Definition
Go to Component Declaration / Entity Declaration / Architecture Declaration
Open Design Breadcrumb Instance
Jump to Assignment
Jump to an Imported File
Jump to a Macro Definition
Jump to State Machine
Comment @see and @link
Show Connected TLM Ports
Show in Config DB View
Show Associated Getters in Config DB View
Show Associated Setter in Config DB View
Show in Factory Overrides View
Show in Registers View
Find All References / Readers / Writers
Show Constraints
Show Instances
Peek
Definition / Declaration
Type Definition
Implementations
References
Content Assist
Context Sensitive
Code Templates
Automatic Instantiation
Override Functions
Implement Extern Functions
Generate Setters and Getters
UVM Field Editor
Override Annotation
Generate Case Statement Using Autocomplete
Refactoring Operations
Rename Symbol
Bind Method Call Arguments by Name / Position
Connect Instance Ports by Name or Position / Expand .* Port Connections
Extract to Variable
Extract to Method or Module / Move Selection to New File
Join / Split to Extern and Implementation
Add Port
Add Parameter
Add New Argument to Method
Remove Argument from Method
Change Position of Method Argument
Breadcrumb
Scope Breadcrumb
Design Breadcrumb
Code Factory
Diagrams
Macros
Inactive Code Highlight
Macro Expansion
Views
Compile Order
Compiled Files
Design Hierarchy
Verification Hierarchy
Outline
Problems
Call Hierarchy
UVM Sequence Tree
Type Hierarchy
Workspace Symbols
Diagnostics
Semantic Search
Code Lens
Expand/Collapse Macro
Show Constraints
Content Filters
Verissimo Integration
DVT AI Assistant
DVT AI Assistant allows you to efficiently interact with Large Language Models (LLMs) to generate new code, explain and improve the existing code, or do any project related tasks.
Checkout Hook
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