SoCBuilder

SoCBuilder is a VS Code extension that enhances SystemVerilog development with automatic declaration alignment and productivity tools for SoC design.

Features

• Align SystemVerilog variable declarations
• Improve RTL readability
• Designed for SoC engineers

Usage

1. Select your code
2. Right click → SoCBuilder: Align Declarations
3. Or use command palette

Example

Before:

logic[7:0]a;
wire b;
reg   [31:0]  data_valid;