VeriFlow - VS Code Extension

简体中文

Overview

VeriFlow is a VS Code extension for Verilog and SystemVerilog projects. It brings module scanning, dependency analysis, simulation execution, waveform opening, and Testbench generation into the VS Code sidebar.

The extension core is implemented in TypeScript, so the VS Code extension itself does not require a Python runtime.

Preview

Quick Start

Requirements

• VS Code 1.80+
• A Verilog simulator, such as:
  • Icarus Verilog - open source, recommended
  • Synopsys VCS
  • Xilinx XSim
  • A custom simulator command
• A waveform viewer (optional), such as:
  • Built-in VeriFlow waveform viewer for .vcd files
  • Surfer - open source, recommended
  • GTKWave
  • A custom waveform viewer command

Installation

Install VeriFlow from the VS Code Marketplace, or install a local .vsix package manually.

Basic Flow

1. Open a folder that contains .v or .sv files.
2. Open the VeriFlow view from the Activity Bar.
3. VeriFlow scans modules automatically and groups them by directory.
4. Click Select Top Module and choose the top module.
5. Click Analyze Dependencies to resolve the compile order.
6. Click Compile & Simulate to run simulation.
7. Click Open Waveform to open the generated waveform file.

You can also open .vcd files directly in VS Code with VeriFlow Waveform Viewer.

Testbench Generator

The Testbench Generator view can generate a Verilog testbench from scanned modules.

Options

Usage

1. Click + in DUT Modules and select the modules to instantiate.
2. Select a DUT module and edit its port connections and parameter values.
3. Configure clocks, reset, waveform, and timeout options.
4. Click Generate Testbench to create and open the testbench file.

Generated testbenches are written to the workspace root by default. Set veriflow.testbenchOutputDir to write them into a workspace-relative subdirectory. VeriFlow creates the directory if it does not exist.

Extension Settings

Sidebar

The sidebar contains two views.

VeriFlow

The title bar actions are:

• Select Top Module - choose the top module from scanned modules
• Analyze Dependencies - analyze dependencies and generate compile order
• Compile & Simulate - compile and run simulation
• Open Waveform - open the configured waveform viewer
• Scan Modules - rescan the workspace

The module list refreshes when the VeriFlow view is opened, when the Testbench Generator is opened, when a testbench is generated, and when workspace files or relevant settings change.

Testbench Generator

This view contains:

• Properties - testbench name and timescale
• Clocks - clock frequency configuration
• Reset - reset polarity and duration
• DUT Modules - module selection, port editing, and parameter editing
• Waveform - waveform file configuration
• Timeout - simulation timeout configuration

Built-in Waveform Viewer

VeriFlow can preview .vcd files inside VS Code.

Ways to open it:

• Open a .vcd file and choose VeriFlow Waveform Viewer.
• Right-click a .vcd file and run Open VCD in VeriFlow Viewer.
• Set veriflow.waveViewer to builtin, then use Open Waveform after simulation.

The current viewer is an early prototype. It supports signal search, time grid, cursor, zoom, pan, single-bit signals, bus signals, and dense waveform aggregation.

Output Panel

Simulation output is written to the VS Code Output panel under the VeriFlow channel.

Messages are grouped by level:

• [INFO] - normal information
• [OK] - successful operation
• [WARN] - warning
• [ERROR] - error message, including file and line references when available

Built-in Simulator Commands

Custom Simulator Example

{
  "veriflow.simulator": "custom",
  "veriflow.simulatorCompileCmd": "verilator --cc --exe --build -j -o {output} {files}",
  "veriflow.simulatorRunCmd": "{output}",
  "veriflow.waveViewer": "custom",
  "veriflow.waveViewerCmd": "gtkwave {wave_file} &",
  "veriflow.libDirs": [
    "/path/to/shared/libs",
    "/path/to/vip"
  ]
}

License

MIT

Feedback

Issues and suggestions are welcome on GitHub Issues.