verilog-testbench-instance README

This extension "verilog-testbench-instance" can be used to enhance verilog programming capability.

Features

It includes two command, Testbench(generate testbench for verilog module in active editor) and Instance(generate instance for verilog module in active editor).

For example if there is active editor of verilog module, you press ctrl+ shift + p to select command:

It will generate the testbench in a new terminal.

Requirements

It need python3 environment.

Extension Settings

This extension contributes the following settings:

• Testbench: generate testbench for verilog module in active editor
• Instance: generate instance for verilog module in active editor

Known Issues

• Install failed: If you failed to install this extension, you may be update your vscode to version 1.23.

It is not known what the other issues are.

Release Notes

The github address: https://github.com/truecrab/VSCode_Extension_Verilog

1.0.0

2018/05/07 The initial version. It can generate testbench and instance for verilog module.

1.0.1

2018/05/07 Fixed README.md.

1.0.2

2018/05/07 Fixed README.md to display figure.

1.0.3

2018/05/07 Delete out in .gitignore for upload out folder.

1.0.5

2018/05/08 Modify the file open operation to fixed decoding problem in China.

Other

Enjoy!