This extension "verilog-testbench-instance" can be used to enhance verilog programming capability.
It includes two command, Testbench(generate testbench for verilog module in active editor) and Instance(generate instance for verilog module in active editor).
For example if there is active editor of verilog module, you press ctrl+ shift + p to select command:
It will generate the testbench in a new terminal.
It need python3 environment.
This extension contributes the following settings:
It is not known what the other issues are.
The github address: https://github.com/truecrab/VSCode_Extension_Verilog
2018/05/07 The initial version. It can generate testbench and instance for verilog module.
2018/05/07 Fixed README.md.
2018/05/07 Fixed README.md to display figure.
2018/05/07 Delete out in .gitignore for upload out folder.
2018/05/08 Modify the file open operation to fixed decoding problem in China.