RapidRTL

Instant HDL to schematic visualisation, directly inside Visual Studio Code. Convert Verilog, SystemVerilog, and VHDL to interactive circuit diagrams with no internet connection required.

This extension bundles open-source synthesis tools (Yosys, GHDL and others). Corresponding source for all GPL-licensed components: rapidrtl.com/oss-source — see License.

Select any logic and press Ctrl+Alt+V. No module header, no entity, no boilerplate — ports, widths and clocks are inferred for you.

Features

• Your RTL never leaves your machine: Synthesis and licence verification run entirely locally using bundled Yosys and GHDL binaries. No source code, filenames, or design data are ever transmitted — see Privacy & Telemetry.
• VHDL, Verilog, and SystemVerilog: Full support for all three major HDL languages.
• Smart Snippet Inference: Write just the logic — RapidRTL automatically infers ports, entity wrappers, and module declarations.
• Projects of Many Files: Rendering a whole file resolves the modules, entities and packages it instantiates from the rest of your workspace and draws them as real submodules with their exact ports. `include files, SystemVerilog package imports and VHDL libraries resolve the same way. Only what genuinely isn't there — vendor IP, files outside the workspace — stays a black box. Click a submodule for its ports and a drawing of what is inside it, then Render it or Open file; the breadcrumb takes you back up. Go to Definition (F12) on a module, entity, component or package opens the file that declares it, and the schematic follows the file you are editing.
• Interactive Schematics: Pan, zoom, and inspect synthesised circuits in a dedicated panel.
• High-Level and Gate-Level Views: Toggle between a high-level view (preserving muxes, adders, and registers) and a gate-level view of primitive gates (AND, OR, NOT).
• Gate-Level Decomposition: See exactly how a cell breaks down into primitive gates. The NAND/NOR/AND-OR-NOT basis switcher is Pro.
• Critical Path: A toolbar button lights the longest logic path, from the register or input where it starts to where it ends, with its depth and each step. On an FPGA target it also says how many of the levels are carry-chain cells or wide muxes, which are much faster than a LUT.
• Block View: View: Blocks draws a module as its always blocks or processes, assignments and instances, with the signals between them. It reads the source, so it works on code that does not synthesise yet. A for-generate is one block with its count (u_ff ×4).
• State Machines: View: State machines draws each state machine in your design as a state diagram: states named as your code names them, every transition labelled with its condition, the reset and the outputs each state drives. Click a state to see where it goes next and when.
• Find a Signal: A search box lists every signal on the schematic; pick one and its wires light up and come into view. Hover any wire to see what it carries.
• Simulation (Pro): Run the schematic clock by clock, on your machine, with no testbench. Every wire shows its value, a waveform in the style of ModelSim's shows the inputs, outputs and registers (an enum by its state names), and you change an input by clicking it. Add the signals inside any submodule, or find one at any depth by name. Ask Why is this x? of an unknown signal, turn a run into checks with expected values, and export it as a VCD or a SystemVerilog or VHDL testbench. Yosys's own simulator does the work, so every cell behaves as synthesised.
• Signal Tracing (Pro): Click any wire or port in the schematic and the editor jumps to the line that drives it (an input jumps to where it is declared). Click a constant and it jumps to where your code writes that value.
• Show in Code (Pro): From a mux, an adder or a register in the cell inspector, jump to the code that built it.
• Reveal in Schematic (Pro): The other way round — select code (an expression, a line, an always block), right-click Reveal in Schematic, and the wires and cells built from it light up and come into view. Put the cursor on a signal name to light up that signal, or on an operator to light the cell built there.
• FPGA Target Mapping (Pro): Map your design onto a real FPGA family — Xilinx 7-Series, Lattice iCE40, Lattice ECP5, Gowin, Intel Cyclone IV, or Intel Cyclone V — and see the primitives it actually uses: LUTs, flip-flops, carry chains, DSP slices, and block RAM. Runs on your own machine in seconds.
• Pin / Compare (Pro): Pin the current result as a baseline (free), change your RTL, and compare — LUTs, flip-flops, DSPs, carry chains, RAM, cell count, logic depth and latch bits, before and after, with the delta. Compare against the committed version of the file (git, Subversion, Mercurial, Perforce, or your own command), the saved copy on disk, or a pin. Then, on demand, ask Yosys to formally check that the two versions are equivalent — a proof, a counterexample, or an honest "unknown", never a guess.
• Live Preview (Pro): Optionally re-synthesise automatically each time a file of the design is saved.

See it work

Simulate the schematic — Pro

Click Simulate and the schematic runs clock by clock, on your machine: every wire takes the colour of its value, and a waveform shows the inputs, outputs and registers, a state register by its state names. Click an input to change it; drag the cursor and the schematic follows.

When a signal is unknown, right-click it: Why is this x? follows the x back to where it starts, here a register with no reset, and lights the way on the schematic. Expected values turn a run into checks, and Export writes it as a SystemVerilog or VHDL testbench.

Projects of many files — free

Render a file and the modules it instantiates come from the rest of your workspace, drawn as blocks with their ports. Click one for a drawing of what is inside it; Render opens its file and draws it, and the breadcrumb at the bottom left takes you back up.

Go to Definition (F12) on a module, entity, component or package opens the file that declares it. The schematic follows the file you are editing; the pin beside the breadcrumb keeps it on one design.

From schematic to code, and back — Pro

Click any wire or port and the editor jumps to the line that drives it: the assign, the declaration that computes it, the first assignment in the register's always block.

Or go the other way: select code, right-click Reveal in Schematic, and the logic it built lights up — the comparator from an ==, the mux from a ?:, the register from an always block.

Gate-level view — free

Drop from high-level cells to the primitive gates underneath. A priority arbiter, decomposed:

State machines — free

View: State machines draws each state machine in your design as a state diagram, with the states named as your code names them. Click a state to see where it goes and when; Show in code (Pro) jumps to its branch:

What your design costs on a real FPGA — Pro

Map the design onto an actual family and see the primitives it consumes. This multiply-accumulate with a 256-byte memory becomes one DSP48E1 and eight distributed RAMs on Xilinx 7-Series — answered in seconds, on your own machine:

Also available for Lattice iCE40, Lattice ECP5, Gowin, Intel Cyclone IV and Intel Cyclone V. Pick the family from the Target selector at the top left of the schematic. These are Yosys mapping estimates, not a substitute for your vendor tool's place-and-route report — and RapidRTL says so on screen.

Inspect any cell

Click a cell to see what it is, why it's there, and how it breaks down into gates:

Errors land on the right line

Synthesis failures map back to your source, as editor diagnostics rather than raw tool output:

VHDL too

Not a Verilog-only tool — VHDL is a first-class citizen, through the same local GHDL pipeline:

Free vs. Pro

RapidRTL for VS Code is free to use for its core workflow — visualising HDL as a schematic, in any of the three supported languages, at both high level and gate level, entirely offline. Whole projects are free too: submodules resolved from across your workspace, Go to Definition, the breadcrumb down and back up the hierarchy, and the block view.

Pro adds the features you'd want once it's part of your daily work: tracing both ways between code and schematic (click a wire to jump to the line that drives it; select code to see the logic it built), simulation on the schematic (every wire's value, clock by clock, with a waveform you drive by clicking, down to the signals inside submodules), FPGA target mapping (what your design costs in LUTs, flip-flops, DSPs and block RAM on a real family), Compare (before/after resource deltas against a committed, saved or pinned baseline, plus the on-demand formal equivalence check), the gate-basis switcher (NOR / AND-OR-NOT as well as NAND), and Live Preview. Locked features are visible wherever you'd normally use them, not buried in Settings, and show what they do when you try them.

Try every Pro feature free for 7 days: run RapidRTL: Start 7-Day Pro Trial, or choose "Try Free for 7 Days" when you click a locked feature. You sign in on rapidrtl.com (Google, GitHub or an email address), and the trial key comes back to VS Code. One trial per account; nothing is charged when it ends. Like a licence, the trial key is checked offline: starting the trial needs the internet once, and your code never leaves your machine.

Pro is a one-time $39 purchase (no subscription): buy it here, or run RapidRTL: Buy Pro from the command palette — locked features also show a "Buy Pro" prompt the moment you try them. Licence verification is fully offline: a key is a signed token checked against a public key compiled into the extension, so unlocking Pro never makes a network call either — see RapidRTL: Enter License Key in the command palette if you already have one.

Privacy & Telemetry

Synthesis runs on bundled Yosys and GHDL binaries on your own machine. Your RTL is written to a temporary directory, synthesised locally, and rendered locally. It is never uploaded, and there is no server to upload it to — which is why RapidRTL works on an air-gapped machine, and why it is usable under an NDA that forbids pasting source into a website. If you pin a baseline, RapidRTL stores that baseline locally in VS Code's workspace-specific extension storage until you clear it; compare results and equivalence verdicts are never persisted anywhere.

RapidRTL Pro never sends anything in the background. The only outbound request a Pro user's extension can make is one they trigger themselves with RapidRTL: Report This Error — and it shows you exactly what will be sent before it sends it.

Free-tier installs additionally send anonymous, event-only usage telemetry — disclosed on first activation and controlled by the rapidrtl.telemetry.enabled setting:

• What's sent by default: activation, synthesis success/failure, language, how many workspace files a render resolved (a count only), which Pro feature (if any) you tried to use, whether you started the 7-day trial and which Pro features you used during it (each at most once a day), and whether VS Code is running locally or in a remote environment — only the kind VS Code reports, such as ssh-remote, dev-container or wsl, never a host name. A random install-scoped UUID identifies events; there is no account, no IP retention, and no fingerprinting.
• What's never sent by default: RTL source, filenames, paths, identifiers, or workspace names. Synthesis-error telemetry sends a locally-classified error category only (e.g. parser_inference, timeout) — never the raw tool output, which routinely embeds source fragments.
• Opt-in exception: rapidrtl.telemetry.includeCodeOnCrash (off by default). If you turn it on, a synthesis-failure event also attaches the RTL snippet that failed — useful if you want to help debugging without doing the manual "Report This Error" flow every time, but it does mean code leaves your machine automatically for as long as it's on. Nothing else changes: the other two gates below still apply, and it's still just that one event type.
• Honours VS Code's own global telemetry switch (telemetry.telemetryLevel) — if that's off, RapidRTL sends nothing, automatically.
• Entering a Pro licence key disables it permanently, including the opt-in above. The 7-day trial is not a licence, so during the trial telemetry stays as you have it set.

The one exception to "never sent automatically" is RapidRTL: Report This Error, available in both tiers: on a synthesis failure, it opens the exact payload — including full tool output and your RTL — in an editor tab for you to review, and sends nothing until you explicitly confirm. Per-incident, explicit, inspectable.

Requirements

• Visual Studio Code 1.80 or later
• Windows (x64), Linux (x64), or macOS 14+ (Apple Silicon)

That's the whole list. Yosys, GHDL, netlistsvg and a Python runtime are all bundled inside the extension, and the schematic renderer runs on the Node runtime already built into VS Code — so you do not need Node.js, Python, or any FPGA vendor toolchain installed.

Usage

Visualise a Selection

1. Open a .vhd, .vhdl, .v, or .sv file.
2. Select the code you want to visualise.
3. Right-click and choose RapidRTL: Visualize Selection, or press Ctrl+Alt+V (Windows/Linux) / Cmd+Alt+V (Mac).

Visualise an Entire File

• Click the play icon in the editor title bar, or
• Right-click anywhere in the file and choose RapidRTL: Visualize File, or
• Press Ctrl+Alt+Shift+V (Windows/Linux) / Cmd+Alt+Shift+V (Mac).

Live Preview

Enable automatic re-synthesis on save via the status bar toggle or through RapidRTL: Toggle Live Preview in the command palette.

Compare before and after (Pro)

1. Visualise a file, then edit it — or just visualise a file that has uncommitted changes.
2. Click Compare in the strip above the schematic (or run RapidRTL: Compare with Baseline…). The baseline defaults to the committed version of the file when the file is under version control (git, Subversion, Mercurial and Perforce are detected; any other tool works through rapidrtl.compare.committedCommand), otherwise to the saved copy on disk. You can also type a revision (a branch, tag or commit) to compare against, or Pin any result as a baseline first — pinning is free and is the only way to compare a selection.
3. Read the table: base / now / Δ / Δ% for LUTs, flip-flops, DSPs, carry chains, block and distributed RAM, SRLs, MUXFs, total cells, logic depth and latch bits — for the FPGA family you have selected, or the generic cell classes otherwise. Both sides are always synthesised under your current settings, so the numbers are like-for-like.
4. Check equivalence asks Yosys to prove the two versions produce the same outputs for every input sequence. The verdict is one of: proven for all inputs, proven under the zero-initial-state model (both designs assumed to reset to zero), no difference found in the first 20 cycles (a bounded search, not a proof), not equivalent with a counterexample you can expand, different ports (nothing to compare), or unknown with the reason (a timeout, an unsupported construct). It never says "equivalent" for anything less than a proof.

With Live Preview on, an active compare refreshes on every save; the equivalence verdict belongs to a specific pair and is cleared when either side changes.

Commands

Configuration

Search for rapidrtl in VS Code Settings (Ctrl+, / Cmd+,).

VHDL Snippet Support

You do not need to write a complete entity and architecture. Write only the logic and RapidRTL will infer the surrounding boilerplate:

signal count : unsigned(7 downto 0) := (others => '0');

process(clk)
begin
  if rising_edge(clk) then
    count <= count + 1;
  end if;
end process;

q <= count;

RapidRTL will infer clk as an input clock port, q as an output port, and generate the complete entity and architecture wrapper automatically.

Troubleshooting

Synthesis produces no output or an error

Open the synthesis log via RapidRTL: Show Synthesis Log in the command palette. The log shows the exact command that was run and any error output from the synthesis tools.

Timeout errors

Synthesis defaults to a 45-second budget (rapidrtl.synthesis.timeoutSeconds). It runs entirely on your own machine rather than a shared server, so if you're on slower hardware or working with a genuinely large design, raise the setting rather than splitting the file.

Bidirectional (inout) ports

The schematic renderer cannot draw bidirectional ports yet. A design using inout fails with a message naming the ports; split the port into separate in/out signals with an enable to visualise the logic around it.

VHDL constructs not supported

File I/O and simulation-only constructs cannot be synthesised.

rapidrtl.vhdl.standard accepts 19, and ordinary VHDL synthesises identically under it — so if your project is configured for VHDL-2019, you can select it and everything behaves as expected. However, the underlying GHDL's VHDL-2019 support is still incomplete: constructs introduced by 2019, such as mode views, currently fail during analysis. VHDL-2008 (08) remains the recommended setting.

Learn

Guides to VHDL, Verilog and SystemVerilog, each with live schematics: rapidrtl.com/learn

Support

For bug reports, feature requests, or general enquiries, contact:

help@rapidrtl.com

By installing and using this extension you agree to RapidRTL's Terms of Service and Privacy Policy.

License

Copyright (c) 2026 TrendyToros Ltd. All Rights Reserved.

The RapidRTL extension itself is proprietary; copying, modification and redistribution are not permitted. See the licence distributed with the extension for full terms.

RapidRTL is distributed together with third-party software — including Yosys, GHDL, netlistsvg and a Python runtime — which is not covered by that licence. Each component remains under its own terms, several of which are free-software licences that grant you rights RapidRTL's licence does not restrict. A full inventory, with licences and upstream sources, is in THIRD-PARTY-NOTICES.md, and the complete licence texts ship inside the extension under bin/<platform>/licenses/.

Corresponding source for the GPL-licensed components bundled in this extension — the exact revisions distributed, including build scripts — is available at rapidrtl.com/oss-source, free of charge, for at least three years from each release.