RapidRTL
Instant HDL to schematic visualisation, directly inside Visual Studio Code. Convert Verilog, SystemVerilog, and VHDL to interactive circuit diagrams with no internet connection required.
Features
- Fully Offline: Synthesis runs locally using bundled Yosys and GHDL binaries. No data leaves your machine.
- VHDL, Verilog, and SystemVerilog: Full support for all three major HDL languages.
- Smart Snippet Inference: Write just the logic — RapidRTL automatically infers ports, entity wrappers, and module declarations.
- Interactive Schematics: Pan, zoom, and inspect synthesised circuits in a dedicated panel.
- Live Preview: Optionally re-synthesise automatically each time a file is saved.
- Gate-Level and High-Level Views: Toggle between a high-level view (preserving muxes, adders, and registers) and a gate-level view (AND, OR, NOT).
- Signal Tracing: Click any net in the schematic to highlight the corresponding signal in the editor.
Requirements
- Visual Studio Code 1.80 or later
- Node.js (required to run the bundled netlistsvg renderer)
No other tools are required. Yosys, GHDL, and netlistsvg are bundled within the extension.
Usage
Visualise a Selection
- Open a
.vhd, .vhdl, .v, or .sv file.
- Select the code you want to visualise.
- Right-click and choose RapidRTL: Visualize Selection, or press
Ctrl+Alt+V (Windows/Linux) / Cmd+Alt+V (Mac).
Visualise an Entire File
- Click the play icon in the editor title bar, or
- Right-click anywhere in the file and choose RapidRTL: Visualize File, or
- Press
Ctrl+Alt+Shift+V (Windows/Linux) / Cmd+Alt+Shift+V (Mac).
Live Preview
Enable automatic re-synthesis on save via the status bar toggle or through RapidRTL: Toggle Live Preview in the command palette.
Commands
| Command |
Description |
| RapidRTL: Visualize Selection |
Synthesise and visualise the selected HDL code |
| RapidRTL: Visualize File |
Synthesise and visualise the entire active file |
| RapidRTL: Toggle Live Preview |
Enable or disable automatic re-synthesis on save |
| RapidRTL: Show Synthesis Log |
Open the synthesis output channel |
Configuration
Search for rapidrtl in VS Code Settings (Ctrl+, / Cmd+,).
| Setting |
Default |
Description |
rapidrtl.vhdl.standard |
08 |
VHDL standard: 87, 93, 00, 02, or 08 |
rapidrtl.schematic.detailLevel |
high |
high preserves muxes and adders; gate shows only primitive gates |
rapidrtl.schematic.readableNames |
true |
Preserve human-readable signal names in the schematic |
rapidrtl.livePreview.enabled |
false |
Re-synthesise automatically when a file is saved |
rapidrtl.livePreview.delay |
1000 |
Debounce delay in milliseconds before auto-synthesis |
rapidrtl.tools.yosysPath |
— |
Override path to Yosys binary (leave empty for auto-detection) |
rapidrtl.tools.ghdlPath |
— |
Override path to GHDL binary (leave empty for auto-detection) |
VHDL Snippet Support
You do not need to write a complete entity and architecture. Write only the logic and RapidRTL will infer the surrounding boilerplate:
signal count : unsigned(7 downto 0) := (others => '0');
process(clk)
begin
if rising_edge(clk) then
count <= count + 1;
end if;
end process;
output <= std_logic_vector(count);
RapidRTL will infer clk as an input clock port, output as an output port, and generate the complete entity and architecture wrapper automatically.
Troubleshooting
Synthesis produces no output or an error
Open the synthesis log via RapidRTL: Show Synthesis Log in the command palette. The log shows the exact command that was run and any error output from the synthesis tools.
Timeout errors
Synthesis is limited to 15 seconds per run. If your design is large, try selecting a smaller section of code rather than the entire file.
VHDL constructs not supported
VHDL-2019 is not currently supported. Use VHDL-2008 (rapidrtl.vhdl.standard: "08"). File I/O and simulation-only constructs cannot be synthesised.
Code size limit
Each synthesis request is limited to 20,000 characters. Break large files into smaller modules if necessary.
Support
For bug reports, feature requests, or general enquiries, contact:
vincenzo.nannetti@trendytoros.com
License
Copyright (c) 2026 Vincenzo Nannetti, TrendyToros Ltd. All Rights Reserved.
This software is proprietary. Copying, modification, and redistribution are not permitted. See the licence distributed with the extension for full terms.
