In FPGA development, ensuring code quality and compliance with project-specific guidelines is a critical yet time-consuming task. While linting tools like Questa Lint (for Verilog/SystemVerilog) help enforce general coding standards, they often fail to address team-specific checklist items or synthesis-related warnings. Additionally, identifying and fixing timing issues such as latch formations and packed/unpacked array range warnings typically require synthesis runs that can take lot of time. To overcome these limitations, I came up with FPGA Error Prediction, a Visual Studio Code extension designed to automatically detect and highlight FPGA-specific coding and synthesis errors during development. This extension provides real-time error squiggles on the exact lines of violations, significantly reducing the time spent on manual reviews and synthesis iterations. Core Functionalities: • Automated Checklist Enforcement: o Developers should be able to define custom coding checklists within the extension as per particular team needs. o The extension automatically scans files and flags violations as squiggles on the exact lines of code. • Synthesis Warning Detection without Running Synthesis: o Identifies potential latch formations, packed/unpacked array mismatches, and other synthesis-related warnings before running synthesis. o Helps developers address design issues early in the coding phase. • Customizable Rule Set: o Teams can modify or extend the checklist dynamically to reflect evolving best practices. o The extension adapts to team-specific guidelines automatically. • Real-Time Code Analysis: o We can run the extension whenever needed( procedure will be explained below). o Provides immediate feedback with error messages and recommendations. • Seamless Integration with VS Code: o Lightweight and fast. o Works directly within the VS Code IDE without requiring external tools (linting tools). ConfigurationTo enable or disable specific FPGA error checks, follow these steps:
Here, you can toggle:
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