Sigasi Studio for Visual Studio Code

Sigasi Studio is an upfront verification IDE that helps hardware designers boost their productivity and creativity with speed, accuracy, and consistency in design entry. Our analysis engine continuously powers through projects, providing precise and immediate feedback that guides users to the root cause of issues, while scaling up to any kind of project. You can explore projects easily with user-friendly navigation. Works with VHDL, Verilog, SystemVerilog, or a mix.

Sigasi Studio for VS Code shares projects seamlessly with our Eclipse plug-in.

Features include: upfront verification (advanced type-time linting), autocomplete, find references, format code, rename refactoring, hierarchy views, offline updates, preprocessor views for Verilog & SystemVerilog, UVM support, and syntax validation.

Please note that in order to enjoy this free extension, you will need a license key. You can request a free trial via our website. Have questions, want a demo, or want to discuss full licensing options? You can email our support or sales team or use our online form.

Sigasi Studio for Visual Studio Code
FAQ
- How do I set up my project?
- Can I use a different java installation to start the extension?

All the power that Sigasi Studio for Eclipse offers, now in VS Code.

Prerequisites

Make sure you have a valid Sigasi XL or XPRT license before starting the extension. Remember that you can always request a trial.
Are you a student or an open source HDL developer? You get a license on the house.

Getting Started

Set the license in the extension settings, File > Preferences > Settings then search for Sigasi > Path To License.

Depending on how your project was set up, you should follow one of the following steps:

I have a project from Sigasi Studio for Eclipse:
- Just open the folder that contains your project
I have a project but no Sigasi VHDL or Verilog support:
- There are two commands available depending on what HDL support you need:
  - Sigasi: Add VHDL Support
  - Sigasi: Add Verilog/SystemVerilog Support
- Note: If you need both you can just run one command after the other
I don't have a project yet:
- You can use the Sigasi: Create New VHDL Project or Sigasi: Create New Verilog Project to create a new project
- If you need mixed language support, you can use the same two commands mentioned above:
  - Sigasi: Add VHDL Support
  - Sigasi: Add Verilog/SystemVerilog Support

Project Setup

We have completely redesigned our existing Project View to be the command center for your HDL projects. Using it, you can change your library mapping as well as the HDL version of your project, folders, and files. You can also add linked files and folders which can be used to link libraries such as UVM for SystemVerilog and Unisim for VHDL without having to copy them directly into your project.

Project Configuration using the Preference View

You can open this view by right clicking an item from the Project View and selecting the option Open the Preference View. This view allows you to configure all the preferences for your project, folder, or file. Change the severity level of the validations, set the include paths and initial defines for SystemVerilog, and modify the conditional variables for your VHDL 2019 projects.
Changes in those preferences will also affect Sigasi Studio for Eclipse users, so if your team uses both products you don't have to worry about duplicating (and maintaining) two or more project configuration formats!

Features that will improve your HDL design experience

Code Completion

Our powerful language server will offer smart suggestions for your HDL code as you type or by pressing Ctrl+Space. Some of these suggestions include entity and component instantiations for VHDL and file browsing for include macros in SystemVerilog.

Code Formatting

Format your code to keep it clean and consistent. We worry about how it looks, so you can focus on designing. You can easily use it by pressing Shift+Alt+F on Windows and Ctrl+Shift+I on Linux.

Find References

Find where an identifier is used, anywhere in your design. You can quickly access this by pressing Shift+F12.

Hierarchy View

Select your top level and browse your design's hierarchy.
Note that this view requires a manual refresh.

Hovers

Just hover your mouse over an identifier to see useful information about every part of your HDL design. For SystemVerilog macros, you can even see the expanded code.

Mark Occurrences

Click on an identifier to highlight all its usages in the current file.

Navigating through your complex design was never this easy. A simple Ctrl+Click on an identifier will take you to where it is declared.

Outline

In the outline, you can see everything that is defined in your file in a very compact and concrete way. Click one of the items to jump to it in your file. You can also enable Follow Cursor such that the view selects the item under your cursor in the outline.

Preprocessor View for SystemVerilog

This view shows a fully expanded (preprocessed) SystemVerilog file.

Rename

Rename allows you to change the name of an identifier across your whole design, this is perfect when you want to change the name of a signal in everywhere.
You can rename something by pressing F2 on the identifier.

Have a question or suggestion?

We greatly appreciate feedback from our users, so don't hesitate to contact our support at support+vscode@sigasi.com

Explore many more features and documentation on Sigasi Insights

FAQ

How do I set up my project?

See our Prerequisites and Getting Started sections.

Can I use a different java installation to start the extension?

Using the Sigasi > Java: Path setting, you can point Sigasi Studio to your custom Java installation. Make sure the path has the right permissions such that Sigasi can execute it and also that the version of the JRE is 11 or 17. Note that you can also use the environment variable JAVA_HOME.

Sigasi for VHDL & SystemVerilog

Sigasi