Sigasi Studio for Visual Studio Code
Sigasi Studio is an upfront verification IDE that helps hardware designers boost their productivity and creativity with speed, accuracy, and consistency in design entry. Our analysis engine continuously powers through projects, providing precise and immediate feedback that guides users to the root cause of issues, while scaling up to any kind of project. You can explore projects easily with user-friendly navigation. Works with VHDL, Verilog, SystemVerilog, or a mix.
Sigasi Studio for VS Code shares projects seamlessly with our Eclipse plug-in.
Features include: upfront verification (advanced type-time linting), autocomplete, find references, format code, rename refactoring, hierarchy views, offline updates, preprocessor views for Verilog & SystemVerilog, UVM support, and syntax validation.
Please note that in order to enjoy this free extension, you will need a license key. You can request a free trial via our website. Have questions, want a demo, or want to discuss full licensing options? You can email our support or sales team or use our online form.
All the power that Sigasi Studio for Eclipse offers, now in VS Code.
Make sure you have a valid Sigasi XL or XPRT license before starting the extension. Remember that you can always request a trial.
Set the license in the extension settings, File > Preferences > Settings then search for
Depending on how your project was set up, you should follow one of the following steps:
We have completely redesigned our existing
Project Configuration using the Preference View
You can open this view by right clicking an item from the Project View and selecting the option
Features that will improve your HDL design experience
Our powerful language server will offer smart suggestions for your HDL code as you type or by pressing
Format your code to keep it clean and consistent. We worry about how it looks, so you can focus on designing.
You can easily use it by pressing
Find where an identifier is used, anywhere in your design.
You can quickly access this by pressing
Select your top level and browse your design's hierarchy.
Just hover your mouse over an identifier to see useful information about every part of your HDL design. For SystemVerilog macros, you can even see the expanded code.
Click on an identifier to highlight all its usages in the current file.
Navigating through your complex design was never this easy. A simple
In the outline, you can see everything that is defined in your file in a very compact and concrete way. Click one of the items to jump to it in your file. You can also enable
Preprocessor View for SystemVerilog
This view shows a fully expanded (preprocessed) SystemVerilog file.
Rename allows you to change the name of an identifier across your whole design, this is perfect when you want to change the name of a signal in everywhere.
Have a question or suggestion?
We greatly appreciate feedback from our users, so don't hesitate to contact our support at firstname.lastname@example.org
Explore many more features and documentation on Sigasi Insights
How do I set up my project?
Can I use a different java installation to start the extension?