Sigasi® Visual HDL™

Want to manage VHDL and SystemVerilog specifications with ease? Sigasi® Visual HDL™ transforms your VS Code workspace into a powerful HDL platform, simplifying and accelerating your workflow.

Use it to design with real-time assistance and introspection. You can easily import existing code—whether from legacy projects, HLS- or AI-generated — and check it and the rest of your project for system and device-based insights. Get instantaneous results on rules in line with functional safety standards (STARC, DO-254, ISO 26262, and the like) or verification methodologies available through UVM, OSVVM, or VUnit. Resolve issues in your designs faster than ever with dynamic (UVM) block and state machine diagrams. Reveal, visualize, and explore the UVM testbench you have in mind. Intuitively discover the connections between ports, the relationships between components, and the topological arrangement using the new UVM Diagram. Navigate effortlessly between diagram and code, digging deeper into the hierarchy as needed, swiftly jumping to declarations, instantiations, and types.

Play with full functionality using our completely free-of-charge Community Edition, as long as your designs have no commercial purposes. It requires Talkback, so you’ll lose your SVH functionality when you lose your internet connection (whether through your ISP or your own firewall).

Do you need to work on a commercial project or do a commercial evaluation? No problem! Our Sales Team will be happy to discuss your options. You can always get in touch with our Support or Sales teams via email or our online form.

Sigasi® Visual HDL™

Prerequisites

Ensure you have a valid Sigasi Designer, Professional, or Enterprise license before starting the extension.
Are you a student or an open source HDL developer? Use our Community Edition.
For commercial use, you can always request a trial.

Getting Started

Set the license in the extension settings, File > Preferences > Settings then search for Sigasi > Path To License.

Depending on how your project was set up, you should follow one of the following steps:

I have a project from Sigasi Visual HDL in Eclipse:
- Simply open the folder that contains your project
I don't have a project yet:
- You can use the Sigasi: New Project... to create a new project

Project Setup

The Sigasi Projects View is the command center for your HDL projects. Using it, you can change your library mapping as well as the HDL version of your project, folders, and files. You can also add linked files and folders which can be used to link libraries such as UVM for SystemVerilog and Unisim for VHDL without having to copy them directly into your project.

Project Configuration

You can configure project-specific settings by right-clicking on the project folder in the Sigasi Projects View, and selecting Configure > Project Settings. The settings view that is opened allows to change the severity level of the validations, set the include paths and initial defines for SystemVerilog, and modify the conditional variables for your VHDL 2019 projects.
Note: file- or folder-specific settings can be configured in the same way, select a folder or file in the Sigasi Projects View and select Configure > File Settings or Configure > Folder Settings.

Features that will improve your HDL design experience

Code Completion

Our powerful language server will offer smart suggestions for your HDL code as you type or by pressing Ctrl+Space. Some of these suggestions include entity and component instantiations for VHDL and file browsing for include macros in SystemVerilog.

Code Formatting

Format your code to keep it clean and consistent. We worry about how it looks, so you can focus on designing. You can easily use it by pressing Shift+Alt+F on Windows and Ctrl+Shift+I on Linux.

Find References

Find where an identifier is used, anywhere in your design. You can quickly access this by pressing Shift+F12.

Design Hierarchy View

Select your top level and browse your design's hierarchy.
Note that this view requires a manual refresh.

Hovers

Just hover your mouse over an identifier to see useful information about every part of your HDL design. For SystemVerilog macros, you can even see the expanded code. Hovers also allow you to quickly perform common actions.

Mark Occurrences

Click on an identifier to highlight all its usages in the current file.

Navigating through your complex design was never this easy. A simple Ctrl+Click on an identifier will take you to where it is declared.

Outline

In the outline, you can see everything that is defined in your file in a very compact and concrete way. Click one of the items to jump to it in your file. You can also enable Follow Cursor such that the view selects the item under your cursor in the outline.

Preprocessor View for SystemVerilog

This view shows a fully expanded (preprocessed) SystemVerilog file.

Block Diagram

Displays a diagram of all architectures, modules, and their instantiations in your current VHDL or SystemVerilog editor. This diagram will automatically update while you are editing your code.

State Machines Diagram

Shows a diagram of state machines in your VHDL or SystemVerilog code from your current editor. This diagram will automatically update while you are editing your code.

Dependencies Diagram

With this diagram, you can visualize the dependencies of your VHDL, SystemVerilog, or mixed-language projects.

Documentation Export

Export the generated documentation in HTML for a project or a top level.

Rename

Rename allows you to change the name of an identifier across your whole design, this is perfect when you want to change the name of a signal in everywhere.
You can rename something by pressing F2 on the identifier.

Have a question or suggestion?

We greatly appreciate feedback from our users, so don't hesitate to contact our support at support+vscode@sigasi.com

Explore many more features and documentation in the manual

FAQ

How do I set up my project?

See our Prerequisites and Getting Started sections.

VHDL & SystemVerilog IDE by Sigasi

Sigasi