Sigasi® Visual HDL™

Do you want to manage VHDL and SystemVerilog specifications more easily? The Sigasi Visual HDL (SVH™) extension lets you do just that by turning your VS code workspace into an HDL platform.

Use it to design with real-time assistance and introspection. You can easily import existing code—whether from legacy projects, HLS- or AI-generated — and check it and the rest of your project for system and device-based insights. Get instantaneous results on rules in line with functional safety standards (STARC, DO-254, ISO 26262, and the like) or verification methodologies available through UVM, OSVVM, or VUnit. Resolve issues in your designs faster than ever with dynamic (UVM) block and state machine diagrams. Reveal, visualize, and explore the UVM testbench you have in mind. Intuitively discover the connections between ports, the relationships between components, and the topological arrangement using the new UVM Diagram. Navigate effortlessly between diagram and code, digging deeper into the hierarchy as needed, swiftly jumping to declarations, instantiations, and types.

Play with full functionality using our completely free-of-charge Community Edition, as long as your designs have no commercial purposes. It requires Talkback, so you’ll lose your SVH functionality when you lose your internet connection (whether through your ISP or your own firewall).

Do you need to work on a commercial project or do a commercial evaluation? No problem! Our Sales Team will be happy to discuss your options. You can always get in touch with our Support or Sales teams via email or our online form.

• Sigasi® Visual HDL™
  • Prerequisites
  • Getting Started
  • Project Setup
  • Project Configuration using the Preference View
  • Features that will improve your HDL design experience
    • Code Completion
    • Code Formatting
    • Find References
    • Hierarchy View
    • Hovers
    • Mark Occurrences
    • Navigation
    • Outline
    • Preprocessor View for SystemVerilog
    • Block Diagram View
    • State Machines View
    • Dependencies View
    • Documentation Export
    • Rename
  • Have a question or suggestion?
  • FAQ
    • How do I set up my project?

Prerequisites

Ensure you have a valid Sigasi Designer, Professional, or Enterprise license before starting the extension.
Are you a student or an open source HDL developer? Use our Community Edition.
For commercial use, you can always request a trial.

Getting Started

Set the license in the extension settings, File > Preferences > Settings then search for Sigasi > Path To License.

Depending on how your project was set up, you should follow one of the following steps:

• I have a project from Sigasi Visual HDL in Eclipse:
  • Simply open the folder that contains your project
• I have a project without Sigasi support:
  • You can use the Sigasi: Add Sigasi Support command to add Sigasi support to your project
• I don't have a project yet:
  • You can use the Sigasi: Create New Sigasi Project to create a new project

Project Setup

We have completely redesigned our existing Project View to be the command center for your HDL projects. Using it, you can change your library mapping as well as the HDL version of your project, folders, and files. You can also add linked files and folders which can be used to link libraries such as UVM for SystemVerilog and Unisim for VHDL without having to copy them directly into your project.

Project Configuration using the Preference View

You can open this view by right clicking an item from the Project View and selecting the option Open the Preference View. This view allows you to configure all the preferences for your project, folder, or file. Change the severity level of the validations, set the include paths and initial defines for SystemVerilog, and modify the conditional variables for your VHDL 2019 projects.
Changes in those preferences will also affect Sigasi Visual HDL for Eclipse users, so if your team uses both products you don't have to worry about duplicating (and maintaining) two or more project configuration formats!

Features that will improve your HDL design experience

Code Completion

Our powerful language server will offer smart suggestions for your HDL code as you type or by pressing Ctrl+Space. Some of these suggestions include entity and component instantiations for VHDL and file browsing for include macros in SystemVerilog.

Code Formatting

Format your code to keep it clean and consistent. We worry about how it looks, so you can focus on designing. You can easily use it by pressing Shift+Alt+F on Windows and Ctrl+Shift+I on Linux.

Find References

Find where an identifier is used, anywhere in your design. You can quickly access this by pressing Shift+F12.

Hierarchy View

Select your top level and browse your design's hierarchy.
Note that this view requires a manual refresh.

Hovers

Just hover your mouse over an identifier to see useful information about every part of your HDL design. For SystemVerilog macros, you can even see the expanded code.

Mark Occurrences

Click on an identifier to highlight all its usages in the current file.

Navigation

Navigating through your complex design was never this easy. A simple Ctrl+Click on an identifier will take you to where it is declared.

Outline

In the outline, you can see everything that is defined in your file in a very compact and concrete way. Click one of the items to jump to it in your file. You can also enable Follow Cursor such that the view selects the item under your cursor in the outline.

Preprocessor View for SystemVerilog

This view shows a fully expanded (preprocessed) SystemVerilog file.

Block Diagram View

Displays a graphical view of all architectures, modules, and their instantiations in your current VHDL or SystemVerilog editor. This view will automatically update while you are editing your code.

State Machines View

Shows a graphical view of state machines in your VHDL or SystemVerilog code from your current editor. This view will automatically update while you are editing your code.

Dependencies View

With this view, you can visualize the dependencies of your VHDL, SystemVerilog, or mixed-language projects.

Documentation Export

Export the generated documentation in HTML for a project or a top-level.

Rename

Rename allows you to change the name of an identifier across your whole design, this is perfect when you want to change the name of a signal in everywhere.
You can rename something by pressing F2 on the identifier.

Have a question or suggestion?

We greatly appreciate feedback from our users, so don't hesitate to contact our support at support+vscode@sigasi.com

Explore many more features and documentation on Sigasi Insights

FAQ

How do I set up my project?

See our Prerequisites and Getting Started sections.