SVEL is used to align logic lines in SystemVerilog code and more.
It makes the rendering prettier and easier to read.
SVEL is currently in version 1.0.0.
Example of using SVEL :
Before using SVEL commands :
module cla{<SIZE>}(
input wire logic [{<SIZE-1>}:0] x,
input logic [{<SIZE-1>}:0] y,
input wire logic cin,
output logic cout,
output logic [{<SIZE-1>}:0] s
);
// declaration des signaux internes :
logic [{<msb-1>}:MACRO{<i>}] var{<i>};
logic [{<msb-1>}:MACRO{<i>}] var{<i>};
logic [{<msb-1>}:MACRO{<i>}] var{<i>};
logic[{<msb-1>}:MACRO{<i>}] var{<i>};
// micro arch
assign val0 = x + y;
assign val1 = x| y;
...
endmodule
After using SVEL Align Without Space :
module cla{<SIZE>}(
input wire logic [{<SIZE-1>}:0] x,
input logic [{<SIZE-1>}:0] y,
input wire logic cin,
output logic cout,
output logic [{<SIZE-1>}:0] s,
);
// declaration des signaux internes :
logic [{<msb-1>}:MACRO{<i>}] var{<i>};
logic [{<msb-1>}:MACRO{<i>}] var{<i>};
logic [{<msb-1>}:MACRO{<i>}] var{<i>};
logic [{<msb-1>}:MACRO{<i>}] var{<i>};
// micro arch
assign val0 = x + y;
assign val1 = x| y;
...
endmodule
After using SVEL Align With Space :
module cla{<SIZE>}(
input wire logic [{<SIZE-1>}:0] x,
input logic [{<SIZE-1>}:0] y,
input wire logic cin,
output logic cout,
output logic [{<SIZE-1>}:0] s,
);
// declaration des signaux internes :
logic [{<msb-1>}:MACRO{<i>}] var{<i>};
logic [{<msb-1>}:MACRO{<i>}] var{<i>};
logic [{<msb-1>}:MACRO{<i>}] var{<i>};
logic [{<msb-1>}:MACRO{<i>}] var{<i>};
// micro arch
assign val0 = x + y;
assign val1 = x| y;
...
endmodule
Before using 2m command:
prod_mask_v2[{<prod>}] = 64'h00000000_0000FFFF << MASK_SHIFT_MUL16;
After using 2m by selecting MASK_SHIFT_MUL16 :
prod_mask_v2[{<prod>}] = 64'h00000000_0000FFFF << {<MASK_SHIFT_MUL16>};
