Neosyn C⏚ for VS Code

Write FPGA hardware in a C-like language, simulate it in seconds, and get clean standard Verilog or VHDL out. C⏚ ("C-Ground") compiles to RTL you can read, review and hand off to any vendor flow — Vivado, Quartus, Libero, or the fully open-source Yosys/nextpnr flow.

This extension is the full toolchain: compiler, cycle-accurate fast simulator, HDL generation, and live views of the state machine and dataflow graph your design actually synthesizes to.

Start a 14-day trial → · Documentation · 10-minute tutorial · Your downloads & license · Open source

Free to install, and installing first is fine — the compiler-backed features ask for a license when you open a .cg file. The trial is three fields and no credit card. Already a customer? Run Neosyn: Open License Portal from the command palette and you land straight on your license page.

Quick start

1. Install Java 17 or newer

The compiler and simulator run on the JVM. This extension bundles the language-server jar, but not a Java runtime — you supply that.

java -version

If that fails or prints 11 or older, install Eclipse Temurin 17 (free, Windows/macOS/Linux) and restart your editor. You can also point the extension at a specific runtime with the neosyn.cg.languageServer.javaPath setting instead of changing your PATH.

2. Get a license

The language server is commercial and machine-bound. A 14-day trial takes three fields and no credit card: neosyn.io/pricing.

Then, in VS Code:

Command palette (Ctrl/⌘ Shift P) → Neosyn: Show Machine Fingerprint. The 64-character hash is copied to your clipboard.
Paste it at neosyn.io/downloads/cg and download your license file.
Command palette → Neosyn: Install License File… and pick it. It is stored at ~/.neosyn/cg.license; VS Code offers to reload.

Neosyn: Open License Portal jumps to step 2 from inside the editor.

3. Check it works

Open any .cg file. You should get live diagnostics and a Neosyn: Fast Simulation (Bytecode) play icon in the editor title bar. Run it — output lands in Output → Neosyn C⏚.

New to C⏚? The ten-minute tutorial builds a 4-bit counter end to end.

What's free, and what the license buys

You never pay for permission to compile.


Free, no license	Syntax highlighting, snippets, file icons. Client-side, always work.
Open source, MPL-2.0	The C⏚ frontend, the Verilog generator, the language server and the runtime library — at github.com/Neosyn-Logic/cg-compiler. Build it yourself and compile forever, no gate. If Neosyn disappears, your designs still build.
Licensed	This prebuilt, signed, supported build · the bytecode Fast Sim · the VHDL backend · FSM and Graph views · production IP cores · updates.

The extension verifies your license before starting the language server. Without a valid license or active trial the server does not start — no diagnostics, no hover, no generation, no simulation. That is off, not degraded. You get a dialog with Install License File…, Show My Fingerprint and Open Customer Portal.

More on the open-core split: neosyn.io/open.

Features

Language intelligence — real-time diagnostics, rich hover (port direction/protocol/type), go-to-definition and find-references across files, document outline and workspace symbols, member completion, folding, inlay type hints, semantic highlighting, and one-click quick fixes that migrate deprecated keywords (sync→push, sync ready→stream, sync ack→confirm).

Fast Sim — cycle-accurate bytecode simulation in seconds, with no HDL toolchain installed and no waveform spelunking. This is the headline feature.

HDL generation — synthesizable Verilog or VHDL, preserving your package layout.

FSM View — renders a task as a state machine, with transitions and conditions, from the compiled design rather than a guess at your source.

Graph View — renders a network and its wiring: bool signals as thin arrows, buses thick with width labels, custom types dashed. Click a node to jump to its definition.

Open-flow integration — drive Verilator lint, Icarus Verilog and GHDL simulation, and Yosys synthesis directly from the editor; generate ready-made Verilator, Yosys and Vivado projects.

For AI agents — cg-agent-kit is a separate MCP server (pip install cg-agent-kit) that hands the same compiler to Claude, Cursor or Windsurf, so an agent writes C⏚ and verifies it against the real toolchain. Setup: neosyn.io/docs/agent-kit.

Commands

All under the Neosyn: prefix in the command palette.

Command	What it does
`Show Machine Fingerprint`	Copy this machine's 64-char hash for licensing
`Install License File…`	Install a `.license` file to `~/.neosyn/cg.license`
`Open License Portal`	Open your account's download/licensing page
`Fast Simulation (Bytecode)`	Cycle-accurate simulation of the current design
`Generate Verilog` / `Generate VHDL`	Emit synthesizable HDL
`Show FSM View` / `Show Graph View`	Visualize the compiled design
`Run Tests`	Run the project's C⏚ test entities
`Synthesize with Yosys`	Synthesis check via the open flow
`Lint Verilog (Verilator)`	Lint the generated Verilog
`Simulate Verilog (iverilog)` / `Simulate VHDL (GHDL)`	Cross-check against an HDL simulator
`Open Waveform Viewer`	Open the generated VCD
`Generate Vivado/Yosys/Verilator Project`	Scaffold a downstream toolchain project
`Restart C⏚ Language Server`	Restart after a config or license change
`Show Output`	Open the Neosyn C⏚ output channel

Settings

Setting	Default	Description
`neosyn.cg.languageServer.javaPath`	`java`	Java executable — set this if Java 17+ is not on your `PATH`
`neosyn.cg.languageServer.path`	`""`	Custom language-server JAR (empty = bundled)
`neosyn.cg.license.path`	`""`	License file (empty = `~/.neosyn/cg.license`)
`neosyn.cg.outputFormat`	`verilog`	Default HDL target
`neosyn.cg.outputDirectory`	`hdl-gen`	Where generated HDL goes
`neosyn.cg.autoGenerate`	`false`	Generate HDL on save
`neosyn.cg.yosys.path` / `iverilog.path` / `verilator.path` / `ghdl.path`	tool name	Paths to open-flow tools
`neosyn.cg.simulation.waveformViewer`	`gtkwave`	Waveform viewer
`neosyn.cg.trace.server`	`off`	LSP trace level, for bug reports

Full list in Settings → Extensions → Neosyn C⏚.

Troubleshooting

Symptom	Cause	Fix
`Could not run Java`	No Java 17+ on `PATH`	Install Temurin 17, or set `neosyn.cg.languageServer.javaPath`
`No license file at …`	Nothing installed yet	Neosyn: Install License File…
Fingerprint mismatch	License belongs to another machine	Rebinding is a support operation — contact us
Expired	Trial or subscription lapsed	neosyn.io/pricing
`UnsupportedClassVersionError`	Java too old	Upgrade to 17 LTS or newer
Imports don't resolve	Package/folder mismatch	A file declaring `package com.example;` must live under `<src>/com/example/` — see project layout

More: neosyn.io/docs/troubleshooting.

Project layout

The compiler expects package names, file names and folder paths to agree:

my-project/
  src/
    com/
      example/
        Counter.cg
        Counter_test.cg

task Counter lives in Counter.cg, which declares package com.example;. Imports use the fully-qualified name: import com.example.Counter;.

License

Commercial software under the Neosyn Software License Agreement — the full text is the License tab of this listing, and LICENSE.md inside the extension. Free to install; a valid license or 14-day trial is required for the compiler-backed features. Site terms · Privacy

C⏚ began as the Synflow Cx toolchain.

Neosyn C⏚ Language

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