MentisHDL

MentisHDL automatically generates technical documentation for Verilog/SystemVerilog files and projects.

Features

• Describes functionality of modules and projects.
• Detects ports, parameters, instances and state machines, and includes descriptions extracted from comments.
• Generates diagrams: module hierarchy and gate-level diagrams

Usage

Create Documentation

Right click → Create Documentation
Generates Markdown documentation (.md) from a selected .v / .sv file or folder.

Live PDF Preview

Ctrl + Shift + V → Preview PDF
Open a live PDF preview of the generated Markdown file.

Export

One-click export to:PDF,Word (.docx) or Markdown (.md)

Commands

Commands should be added as comments in the code.

@detailed

Put above modules that should not be shown as black boxes.

Example:

//@detailed
cve2_if_stage if_stage_i (
  ...
);

@highlight_one(name_of_the_signal)

Highlights only the connection which drives input to the specific module.

Example:

//@highlight_one(clk_i)
cve2_if_stage if_stage_i (
  .clk_i (clk_i),
  .rst_ni(rst_ni),
);

@highlight_all(name_of_the_signal)

Highlights all connections of the specified signal.

Example:

//@highlight_all(clk_i)
cve2_if_stage if_stage_i (
  .clk_i (clk_i),
  .rst_ni(rst_ni),
);

@with_params

Include parameters in the generated symbol.

Use this command only above a top module instance.

Example:

//@with_params
module cve2_counter #(
  parameter int CounterWidth = 32,
  parameter bit ProvideValUpd = 0
)
...

Contact

If you find any bugs or have suggestions for future updates, contact us at:
design@blueprintrtl.com