SynthesisDeck

Open-source FPGA development toolchain for VS Code

Build, simulate, and program FPGA designs without leaving the editor.
SynthesisDeck brings a complete open-source hardware workflow to VS Code — from writing HDL to flashing your board.

Highlights

• One-click synthesis — Yosys → nextpnr → bitstream pack, no Makefiles needed
• Zero-install native toolchain — the pinned oss-cad-suite downloads automatically on first build; no Docker, no manual installs
• Multi-family — iCE40, ECP5, and Gowin (9 board presets)
• Mixed HDL — VHDL (2008), Verilog, SystemVerilog, or any combination
• Board programming — Flash connected FPGAs directly from the editor
• Build Progress Panel — Real-time cyberpunk-themed GUI for pipeline status
• Project scaffolding — Templates with pre-configured constraints and example designs
• Simulation — GHDL testbench execution from the command palette
• PLL generation — Generate PLL configs for iCE40 with icepll

Supported Boards

Quick Start

Prerequisites

First Project

1. Install SynthesisDeck from the Marketplace
2. Open the Welcome page — Ctrl+Shift+P → SynthesisDeck: Welcome
3. System diagnostics will check the FPGA toolchain and programmer status
4. Click New Project, pick a board, choose a template
5. Hit Build & Program to synthesize and flash

Workspace Marker

SynthesisDeck activates when it finds a .synthesisdeck/ directory alongside your fpga-project.toml. New projects get this automatically; for existing projects the extension will prompt you to migrate.

Project Config

[project]
name = "my_project"

[target]
family = "ice40"
device = "hx1k"
package = "tq144"
board = "icestick"

[sources]
top = "top"
vhdl = ["src/*.vhdl"]

Commands

All commands are available via Ctrl+Shift+P (prefix: SynthesisDeck).

Settings

Diagnostics

Built-in problem matchers surface errors directly in the Problems panel:

• GHDL — VHDL errors with file, line, column
• Yosys — Synthesis errors and warnings
• nextpnr — Place-and-route errors

Click any error to jump to the source location.

Constraint Formats

Platform Support

VHDL on Windows uses a standalone GHDL downloaded alongside the suite. VHDL on linux-arm64 is not yet available (Verilog/SystemVerilog works).

Toolchain

SynthesisDeck integrates these open-source tools:

License

MIT

SynthesisDeck bundles and downloads third-party open-source software (openFPGALoader, the oss-cad-suite toolchain, GHDL, libusb/libftdi1, …). See THIRD-PARTY-NOTICES.md for their licenses and sources.