Teven — RTL hierarchy, tracing and waveforms for Verilog and SystemVerilog

Teven brings a design browser and simulation debugger for Verilog and SystemVerilog into VS Code. Build a database from your RTL, then walk the design hierarchy, see every signal of an instance, double-click a signal to jump to the logic that drives it across any number of hierarchy levels, and view your simulation's waveforms.

• Browse the design hierarchy and every signal of an instance
• Trace drivers and loads through the hierarchy with a double-click
• Debug simulations: view waveforms (VCD and FST) beside the code
• Syntax highlighting and code folding for Verilog and SystemVerilog

Features

• Design hierarchy in the activity bar. Expand instances level by level (big designs load on demand). Click an instance to open its module; right-click for Go to Instantiation and Copy Hierarchical Path.
• Double-click a signal to trace its drivers. Teven follows ports up and down the hierarchy to the real logic. One driver jumps straight there, with every line of the always block that drives it selected; several drivers give a list to pick from. Right-click for Trace Driver and Trace Load. x[3] and x[7:0] trace just those bits, and reg2hw.ctrl.en.q traces just that struct field.
• Clickable code. Signals, parameters and struct fields show a hand cursor. A connection's port name (.clk_i(...)) is dimmed, because it belongs to the child module, not to this one. Double-clicking a parameter shows its value in that instance.
• Signals window next to the code, listing every signal of the selected instance: direction, type, width, driver and load counts, and remarks (undriven, multi-driven, unloaded). You can filter and sort it. Double-click a signal to trace it.
• Compile Files or Filelist: one button for a filelist (.f), source files or folders. Each is syntax-checked with slang, like a simulator compiles, with errors in Problems, and joins the design. Then Elaborate builds the database.
• Start from the top file alone. Modules not compiled yet are black boxes in the hierarchy. Right-click one → Compile File for This Module…, then Re-elaborate fills it in.
• Design Files view: the files of your design, grouped by the filelist they come from, with their compile status. Files you add later show as new until you elaborate them in. Your own filelists are never changed. Export Filelist of the Database writes everything the open database was built from, including files added here, as one .f with absolute paths.
• Re-elaborate. When a design file changes, Teven warns you; Re-elaborate rebuilds the open database the way it was built, with any files you added, and reloads it, keeping your place.
• Debug simulations: view waveforms (VCD and FST). Open a .vcd or .fst file and it shows in Teven's waveform viewer: add signals from the dump, zoom, cursors and markers, radix, groups, and save and load the setup. A design database must be open, so the dump's signals map to the RTL.
• Verilog and SystemVerilog syntax highlighting, in dark and light themes, and code folding of modules, functions, tasks and begin / end blocks.

Getting started

1. Open the folder that has your RTL.
2. Click the Teven icon in the activity bar.
3. Choose Compile Files or Filelist… and pick your filelist, or your .sv / .v files (or right-click them, or a folder, in the Explorer). They are syntax-checked.
4. Choose Elaborate and pick the top module from the list (or type it). The database (.ddb) is built and opened. Next time, Open Database… reopens it, or the extension reopens the last one by itself.
5. Expand the hierarchy, open a module and double-click a signal.

To add files to an open design later, compile them the same way and choose Elaborate.

Free edition

This edition is free for personal and commercial use. It opens designs of up to 20,000 instances. For a bigger chip, open a sub-block: build the database with a lower top module.

Teven Pro (coming soon)

Teven Pro adds:

• No design size limit: open full chips.
• Signals from the design into the waveform: drag a signal from the Signals window or the code onto the waveform, or right-click it → Add to Waveform. Drag an instance from the hierarchy to add its signals, the ones the Signals window's filters show (by default its ports), as a group.
• From the waveform to the code: jump from a signal in the waveform to the logic that drives it.
• Black boxes for tracing: list modules such as clock muxes or synchroniser cells, and traces stop at their ports instead of going inside.

Every user will get a free 30-day Pro trial.

Settings

Supported platforms

macOS on Apple silicon (M1 or newer). Linux and Windows are planned.

Feedback

Use the Marketplace page's Q & A and Rating & Review tabs.

Teven is proprietary software, free to use under its licence (the License tab of this page). Third-party components are listed in THIRD_PARTY_NOTICES.md, installed with the extension.