Run Verilog

Run Verilog testbenches with Icarus Verilog and open VCD waveforms in GTKWave from the VS Code editor title bar.

This first release targets Windows and .v testbenches. It does not install Icarus Verilog or GTKWave, modify your testbench, or infer a top-level module.

Requirements

VS Code 1.85.0 or newer on Windows.
iverilog.exe, vvp.exe, and gtkwave.exe available on PATH, or configured with absolute paths in the Run Verilog settings.
A testbench that creates its own VCD file, for example:

initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, tb);
    // Stimulus...
    [#100](https://github.com/Hanying5/run-verilog/issues/100) $finish;
end

Always terminate a testbench with $finish. If a simulation does not terminate, use the Stop Testbench button that replaces Run while the process is active.

Usage

Run a testbench

Open a .v testbench.
Click Run Testbench (play icon) in the editor title bar.
Review compiler and simulation logs in the Run Verilog Output channel.
After a successful simulation, choose one VCD generated or updated by that run. The first item, Do not open a waveform, leaves GTKWave closed.

Only the selected waveform is opened. If the simulation did not create or update a matching VCD, the extension reports that no waveform was found.

View an existing VCD

Open a .vcd file and click View VCD in the editor title bar. The active file is passed directly to GTKWave.

Add DUT source files

The active testbench is always passed to iverilog. Additional sources are configured with workspace-relative globs:

{
  "runVerilog.sourceGlobs": [
    "rtl/**/*.v",
    "sim/models/*.v"
  ],
  "runVerilog.compilerArgs": [
    "-g2012",
    "-I",
    "include"
  ]
}

When the testbench is not inside an open workspace, source and waveform globs are relative to the testbench directory.

Select sources for one simulation

When runVerilog.sourceGlobs is empty, clicking Run Testbench opens a source menu with three choices:

Sources are included in the testbench — compile only the active testbench, for example when it uses `include directives.
Select source files — select one or more .v files in the Windows file picker.
Select source folders — select one or more folders; all .v files below those folders are included recursively.

File and folder selections apply only to the current simulation and do not change workspace settings. Cancelling either picker cancels the run safely. When sourceGlobs contains at least one pattern, the configured patterns are used directly and this menu is skipped.

Settings

Setting	Default	Purpose
`runVerilog.iverilogPath`	`iverilog`	Icarus Verilog compiler executable.
`runVerilog.vvpPath`	`vvp`	Icarus Verilog runtime executable.
`runVerilog.gtkwavePath`	`gtkwave`	GTKWave executable.
`runVerilog.sourceGlobs`	`[]`	Additional `.v` sources relative to the project root.
`runVerilog.sourceExcludeGlob`	`/{.git,node_modules,.run-verilog}/`	Exclusions for source and waveform discovery.
`runVerilog.compilerArgs`	`[]`	Arguments placed before `-o` and source paths.
`runVerilog.simulatorArgs`	`[]`	Arguments placed before the compiled `.vvp` path.
`runVerilog.gtkwaveArgs`	`[]`	Arguments placed before the selected VCD path.
`runVerilog.buildDirectory`	`.run-verilog`	Directory containing per-testbench `.vvp` output.
`runVerilog.promptForWaveform`	`true`	Show the post-simulation waveform picker.
`runVerilog.waveformGlobs`	`["*/.vcd"]`	VCD files considered by the picker.

Executable settings accept either command names resolved through PATH or absolute paths, including paths containing spaces. Processes are started without a command shell.

Commands

Run Verilog: Run Testbench
Run Verilog: Stop Testbench
Run Verilog: View VCD

Build and test

Install Node.js and npm, then run:

npm install
npm run check
npm run test:smoke
npm run test:integration
npm run package:vsix

test:smoke uses the real iverilog and vvp commands on the included fixture. The VSIX is generated as run-verilog-0.2.2.vsix.

Install the VSIX

From VS Code, run Extensions: Install from VSIX... and select the generated file, or use:

code --install-extension .\run-verilog-0.2.2.vsix --force

Marketplace publisher: hanying. Repository: Hanying5/run-verilog.

License

MIT. See the included LICENSE file.