FPGA Workbench Pro - Professional FPGA Development for VS Code

🚀 Features

Complete FPGA Development Workflow

• Multi-Toolchain Support: Xilinx Vivado/ISE, Intel Quartus, Lattice Diamond/Radiant, Open-source (Yosys/nextpnr)
• Advanced Synthesis & Implementation: Full control over synthesis, place-and-route, and bitstream generation
• Integrated Simulation: Support for IVerilog, Verilator, ModelSim, Xsim, and GHDL
• Waveform Viewing: Seamless integration with GTKWave, ModelSim, and Vivado
• Constraint Management: Visual XDC/SDC/PCF constraint editing and validation
• Timing Analysis: Real-time timing reports with slack analysis
• Resource Utilization: Live utilization charts for LUTs, FFs, BRAM, DSP
• Power Analysis: Detailed power consumption reports
• Device Programming: One-click FPGA programming with multiple programmer support

Professional Development Environment

• Project Explorer: Organized view of design sources, constraints, simulation files, and IP cores
• Design Hierarchy: Visual representation of module hierarchy
• Smart Constraint Templates: Auto-generated constraint files for 15+ popular dev boards
• Multi-Board Support: Pre-configured profiles for Xilinx, Lattice, Intel, and Gowin FPGAs
• Build Automation: Parallel build jobs with intelligent dependency management
• Real-time Linting: Verilator/Slang integration for instant syntax checking
• Error Navigation: Click-through from build errors to source code

Supported Development Boards

📦 Installation

From VSIX

code --install-extension haiphan-fpga-workbench-1.0.0.vsix

From Source

git clone https://github.com/HaiPhan285/fpga_extension.git
cd fpga_extension
npm install
npm run compile
npm run package
code --install-extension haiphan-fpga-workbench-1.0.0.vsix

🎯 Quick Start

1. Install FPGA Toolchain

The extension supports multiple toolchains. Choose one:

Open-Source Toolchain (Recommended for beginners)

# The extension can auto-download and configure
# Or manually: https://github.com/HaiPhan285/FPGA_Compiler-

Xilinx Vivado

# Set path in settings: fpgaExtension.vivadoPath
# Example: /opt/Xilinx/Vivado/2023.2

Intel Quartus

# Set path in settings: fpgaExtension.quartusPath

2. Create New Project

1. Open Command Palette (Ctrl+Shift+P)
2. Run: FPGA: Create New FPGA Project
3. Select target board
4. Choose toolchain

3. Configure Your Design

1. Add your Verilog/SystemVerilog/VHDL sources
2. Set top module: fpgaExtension.topModule
3. Select target board: fpgaExtension.board
4. Add constraints (XDC/SDC/PCF)

4. Build & Program

1. Synthesize: Click "Run Synthesis" in FPGA sidebar
2. Implement: Click "Place & Route"
3. Generate Bitstream: Click "Generate Bitstream"
4. Program Device: Click "Program Device"

⚙️ Configuration

Essential Settings

{
  "fpgaExtension.toolchain": "opensource",
  "fpgaExtension.board": "nexys_a7_100",
  "fpgaExtension.topModule": "top",
  "fpgaExtension.clockFrequency": 100.0,
  "fpgaExtension.simulationTool": "iverilog",
  "fpgaExtension.waveformViewer": "gtkwave"
}

Advanced Settings

{
  "fpgaExtension.optimizationGoal": "balanced",
  "fpgaExtension.parallelJobs": 4,
  "fpgaExtension.enableTimingAnalysis": true,
  "fpgaExtension.enablePowerAnalysis": true,
  "fpgaExtension.keepIntermediateFiles": true,
  "fpgaExtension.lintOnSave": true
}

🎓 Usage Guide

Running Simulations

1. Create testbench file (e.g., design_tb.v)
2. Open Command Palette → FPGA: Run Simulation
3. Select testbench
4. View results in output channel
5. Click FPGA: View Waveform to open GTKWave

Managing Constraints

1. Navigate to Constraints panel
2. Click + to add timing constraint
3. Specify clock signal and frequency
4. Run FPGA: Validate Constraints
5. View timing reports after implementation

Viewing Reports

Reports panel shows:

• Utilization: LUT, FF, BRAM, DSP usage
• Timing: WNS, TNS, clock domain analysis
• Power: Total/dynamic/static power breakdown
• DRC: Design rule violations

Device Programming

Supported programmers:

• openFPGALoader (default)
• Vivado Hardware Manager
• Quartus Programmer
• iceprog (iCE40)
• ecpprog (ECP5)

🏗️ Architecture

This extension integrates with your existing FPGA toolchain and wraps:

• Build Scripts: setup.sh, doctor.sh, build.sh
• Synthesis Tools: Yosys, Vivado, Quartus
• P&R Tools: nextpnr, Vivado, Quartus
• Programmers: openFPGALoader, Vivado, others

Base repository: https://github.com/HaiPhan285/FPGA_Compiler-

🎯 Goals

Professional FPGA development environment providing:

1. Download & configure toolchains
2. Verify build environment
3. Run synthesis with optimization control
4. Implement design (place & route)
5. Generate bitstream
6. Program target device
7. Run simulations & view waveforms
8. Analyze timing & power
9. Manage constraints
10. View detailed reports

📋 Command Reference

Build Commands

Simulation Commands

Analysis Commands

Project Commands

🎨 UI Overview

The extension provides a professional sidebar in VS Code:

FPGA Activity Bar

• Dashboard: Quick actions and status
• Project Explorer: Design files organization
• Design Hierarchy: Module tree view
• Constraints: Timing/pin assignments
• Reports: Build results and analysis

🔧 Troubleshooting

Common Issues

Toolchain not found

Solution: Set correct path in settings
- fpgaExtension.vivadoPath
- fpgaExtension.quartusPath  
- fpgaExtension.repoPath (for open-source)

Synthesis fails

Check:
1. All source files are listed
2. Top module is correctly specified
3. No syntax errors (enable linting)
4. Include paths are set correctly

Timing not met

Actions:
1. Review timing report for critical paths
2. Adjust clock frequency constraints
3. Change optimization goal to "speed"
4. Add pipeline stages to critical logic

Bitstream generation fails

Check:
1. Constraint file includes all I/O pins
2. Pin assignments match board layout
3. No DRC violations
4. Sufficient FPGA resources

🤝 Contributing

Contributions welcome! This extension is designed to support the FPGA development community.

Development Setup

git clone https://github.com/HaiPhan285/fpga_extension.git
cd fpga_extension
npm install
code .

Press F5 to launch extension development host.

Adding New Boards

Edit src/boardManager.ts:

your_board: {
  id: "your_board",
  name: "Your Board Name",
  vendor: "Vendor",
  family: "FPGA Family",
  part: "part-number",
  // ... other properties
}

Adding New Toolchains

Implement toolchain interface in synthesis/implementation handlers.

📄 License

MIT License - See LICENSE file

🙏 Acknowledgments

• Built on top of FPGA_Compiler-
• Inspired by ESP-IDF VS Code extension
• Uses open-source tools: Yosys, nextpnr, openFPGALoader
• Community contributions and feedback

📞 Support

• Issues: GitHub Issues
• Documentation: See Wiki

🗺️ Roadmap

• [ ] Hardware-in-the-loop debugging
• [ ] ChipScope/SignalTap integration
• [ ] Block design visual editor
• [ ] IP catalog browser
• [ ] Multi-project workspace support
• [ ] Cloud build support
• [ ] RISC-V soft-core templates
• [ ] Automatic clock domain crossing checks