Crisp — AI Coding Assistant for HDL Engineers

Crisp accelerates digital design and verification by taking you from natural‑language intent to simulated waveforms inside VS Code. It generates synthesizable RTL and verification code, aligns to your project’s coding style, produces vendor run scripts, runs the simulation, and opens the waveform viewer — all in one place.

https://crispaidesign.com

Key features

• End‑to‑end code generation to waveform generation
  • From spec → RTL + testbench → compile/run → waveform — executed from a single prompt.
• Built‑in waveform viewer
  • Inspect VCD/FST/FSDB (FSDB with utility) traces with hierarchical signals, cursors, and measurements directly in the editor.
• Align coding style with your project
  • Learns your naming, formatting, and module/testbench structure from the repo to keep diffs clean.
• Optimized coding for RTL and testbench
  • Generates synthesizable RTL and high quality of SystemVerilog/UVM testbench.
• RTL to spec, and spec to test
  • Generates spec from design, test plan and scenario from spec, and complete testbench for functional coverages.
• Generate run scripts for commercial vendors
  • Creates ready‑to‑run scripts for common simulators and flows; you keep using your preferred tools and licenses.

What Crisp does for you

1. Understands your intent

• Paste requirements or point to a spec; Crisp infers module interfaces, protocols, timing, and corner cases.

2. Generates high‑quality RTL and verification code

• Produces synthesizable Verilog/SystemVerilog or VHDL, plus a matching testbench with stimulus, checks, and assertions.

3. Builds and runs your simulation

• Assembles file lists, flags, include paths, and defines. Runs the simulator, captures logs, and emits VCD/FST.

4. Opens an integrated waveform viewer

• Auto‑loads signals, Annotate waveform values to signals, applies basic colorization/grouping, and drops markers on key events and assertions.

5. Iterates fast

• Update your prompt or edit code, then re‑run. Crisp keeps context and focuses on diffs to minimize churn.

Supported languages

• Verilog, SystemVerilog (RTL + testbench)
• VHDL (RTL + basic testbench)

Script generation and simulators

Crisp can generate run scripts and project files for popular tools. Use is optional — you can keep your existing flow.

• Siemens Questa/ModelSim (do/tcl)
• Cadence Xcelium (xrun)
• Synopsys VCS (vlogan/vcs/simv)
• Aldec Riviera‑PRO (do/tcl)
• Verilator (C++/Makefile harness)
• Icarus Verilog (iverilog/vvp)

Notes

• Commercial tools require you to have valid licenses and installations. Crisp only generates scripts and does not ship vendor binaries or licenses.
• You can customize compile/sim flags, timescales, file lists, and top modules per project.

Style alignment: keep your repo’s voice

Crisp analyzes your repository to match naming conventions, reset polarity, clocking, formatting, and directory layout.

• Adapts to .editorconfig, lint configurations (e.g., Verible/Verilator), and your existing modules/tests
• Honors preferred patterns: synchronous resets, parameterization, interface bundling, UVM/no‑UVM, etc.
• Produces minimal diffs by following your header/license templates and comment style

Tip: Keep representative RTL and testbench files in the repo; Crisp learns more accurately with good examples.

Built‑in waveform viewer

• Load VCD/FST/FSDB with utility from any run
• Hierarchical signal browser with search and pin‑to‑view
• Cursors, measurements, and bookmarks for debug
• Auto‑add clocks, resets, and top‑level I/O; optional signal groups for buses and interfaces
• Annotate waveform values to code editor.

Quick start

1. Install the Crisp extension in VS Code.
2. Open your HDL project folder (Verilog/SystemVerilog/VHDL).
3. Open the Crisp panel and describe what you want to build, e.g., “A parameterizable AXI‑Stream FIFO with first‑word‑fall‑through.”
4. Review the proposed RTL and testbench changes; accept to apply.

That’s it — iterate by editing requirements, code, or prompts, then re‑run.

Configuration and customization

• Project structure: Configure RTL/testbench roots and file‑list patterns.
• Sim flags: Timescale, defines, include dirs, top module, and duration.
• Style: Naming, header template, reset polarity, preferred constructs.
• Artifacts: Output directories for logs, waves, and generated scripts.

All settings can be adjusted per‑project; Crisp remembers your choices.

FAQ

• Do I need commercial tools?

  • No. Crisp can run fully with open‑source tools (Verilator, Icarus). If you have commercial tools, Crisp will generate scripts for them.

• Can Crisp modify my code?

  • Yes, but only after you review and approve the diff. You’re always in control.

• Does Crisp understand my existing testbenches?

  • Crisp includes advanced project and folder anlysis features to understand your workspace to enhance your codebase.