Ashling VS Code Extension for Altera FPGAs Software Development
Welcome to Ashling VS Code Extension for Altera FPGAs software development. This extension is designed for seamless debugging of baremetal applications running in Altera FPGAs Arm HPS and Nios V soft cores.
Features
Configure debugging through a GUI: GUI based debug configurations (like probe selection, device selection, core selection etc) for Altera FPGAs Arm HPS and Nios V soft cores.
Auto-detects and displays all the devices: Auto-detect and display all the devices and cores in the FPGA, allowing user to select the required core for the debug session.
CMake based project support: CMake based project management support, allowing for the direct import and build of Nios V HAL and BSP projects.
Arm HPS and Nios V core run-time debug support: Altera FPGAs Arm HPS and Nios V soft cores (Nios V/g, Nios V/m, Nios V/c) basic baremetal run-time debug support including software and hardware breakpoints using USB-Blaster II.
Run-time debug views: Includes all basic run-time debug views such as Register view, Disassembly view, Memory view, Breakpoint view, Variable view and Peripheral register view.
Custom instruction support: UI option to browse custom instruction XML file for RISC-V launches.
RTOS aware debug views: Supports FreeRTOS and Zephyr RTOS aware debug including views like Thread list, Semaphores, Mutex via Embedded Tools.
QEMU debug support: QEMU simulator based debug support including GUI based debug launch configuration.
WSL support: Debug in WSL environment (Binaries installed in WSL and debugging using host VS Code).
Nios V BSP and application generation support: Supports generation of Nios V BSP and application projects.
Source code Mapping: Allows easy source path remapping when source files are not present in the build/compilation location.
Getting Started
For getting started, refer to the APB226-VSCodeExtForAlteraFPGAs.pdf.
Ensure the Altera® Quartus® Tools and Ashling RiscFree IDE (24.4.1 or later) are already installed in the machine.
