UVM Generator

Generate a SystemVerilog/UVM verification environment directly from VS Code — no more hand-editing template files or running a separate desktop GUI.

This extension is the frontend for a template-based UVM generation engine. It reuses a fixed, proven UVM class/package structure (agent, driver, monitor, sequencer, scoreboard, coverage, SVA, reset sequence) and Questa flow; it does not invent a new UVM architecture, and it does not silently change your project layout.

What this extension does — and does not do

It generates the verification environment, not your design. Running UVM: Generate Testbench creates a complete UVM testbench (interface, agent, driver, monitor, sequencer, scoreboard, coverage, sequence item, test, and Questa run.do) around a design name you provide.

It does not generate, modify, or analyze your RTL/DUT. You must supply your own DUT source file(s) and connect them yourself:

1. Add your DUT file(s) (e.g. spi.v / spi.sv) into the generated <design>_uvm/ folder (or point to them from src_files.list).
2. Instantiate your DUT's actual ports in <design>_top.sv (marked with a /*put your variables*/ placeholder) and add your DUT's signals to <design>_interface.sv.
3. Run UVM: Update Source List so src_files.list picks up the file you added.

Features

• UVM testbench generation — UVM: Generate Testbench creates a complete, ready-to-compile <design>_uvm/ project from your design name.
• Active/passive agent support — choose whether the generated agent drives the DUT (active) or only monitors it (passive); the driver and sequencer are omitted automatically for passive agents.
• Selective generation — pick exactly which components to generate (agent, driver, monitor, scoreboard, coverage, SVA, reset sequence, Questa run.do, ...). Defaults match the full original project.
• Sequence item generation — describe your transaction as a list of name: width fields and get a randomizable uvm_sequence_item back.
• Basic sequence generation — generate a sequence compatible with your sequence item and have it wired into the test's run_phase automatically.
• Source-list management — src_files.list is generated from the files that actually exist in the project, and can be regenerated on demand with UVM: Update Source List.
• Testbench validation — UVM: Validate Testbench runs a lightweight structural check (expected files present, no leftover placeholders, src_files.list references resolve, package imports resolve).
• Questa integration — UVM: Run Questa Simulation runs the generated project's run.do in an integrated terminal.

Requirements

• Python 3.8+ on PATH (or configured via uvmGenerator.pythonPath). The generation engine is a pure-Python package with no third-party dependencies, and is bundled with the extension — you don't install it separately, but a Python interpreter must already be available on your machine.
• Questa/ModelSim is only required for UVM: Run Questa Simulation. All other commands work without a simulator installed. No other simulator is supported yet.

Installation

1. Open the Extensions view in VS Code (Ctrl+Shift+X).
2. Search for UVM Generator.
3. Click Install.

Usage

1. Open your SystemVerilog project folder in VS Code.
2. Open the Command Palette (Ctrl+Shift+P).
3. Run UVM: Generate Testbench.
4. Enter the design name (e.g. spi).
5. Choose Active or Passive agent type.
6. Choose which components to generate (defaults to everything).
7. The project is generated at <workspace>/<design>_uvm/.

spi_uvm/
├── spi_interface.sv
├── sva.sv
├── spi_confg.sv
├── spi_seq_item.sv
├── reset_seq.sv
├── spi_sequencer.sv
├── spi_driver.sv
├── spi_monitor.sv
├── spi_agt.sv
├── spi_scoreboard.sv
├── spi_coverage.sv
├── spi_env.sv
├── spi_test.sv
├── spi_top.sv
├── run.do
└── src_files.list

At this point the environment compiles, but has no DUT and no stimulus — see What this extension does — and does not do above for connecting your own design.

Then, from the Command Palette:

• UVM: Validate Testbench — sanity-check the generated (or hand-edited) project.
• UVM: Update Source List — regenerate src_files.list after adding files (e.g. your own DUT source, or a hand-written sequence).
• UVM: Generate Sequence Item — describe transaction fields and overwrite <design>_seq_item.sv with a randomizable version.
• UVM: Generate Basic Sequence — generate <design>_basic_seq.sv and wire it into the test.
• UVM: Run Questa Simulation — run run.do for the project in a terminal.

Configuration

All diagnostic output (including the exact commands run) is logged to the UVM Generator output channel (View → Output → "UVM Generator").

Limitations

• Questa/ModelSim only. No other simulator is currently integrated.
• You still connect your own DUT. The extension does not parse RTL or infer ports; <design>_top.sv and <design>_interface.sv need your DUT's actual port list filled in by hand.
• Sequence item / basic sequence generation is intentionally simple — a flat list of randomizable fields and a sequence that sends N randomized items. It's a starting point, not a protocol-aware transaction modeler.
• Validation is structural, not a compiler. UVM: Validate Testbench checks that expected files exist, that no template placeholders were left unresolved, and that file references (src_files.list, package imports) resolve. It does not compile or elaborate your design — use your simulator for that.
• Requires a local Python interpreter. The extension does not bundle or install Python itself.

More information

Full architecture notes, the Python CLI, and the test suite for the generation engine live in the project's source repository.