UVM Generator

Ahmed Nossier
LinkedIn · Contact

Generate a reusable SystemVerilog/UVM verification environment directly from VS Code using a fixed, reusable UVM template set.

🎥 Demo

UVM Generator — VS Code Extension Demo

Watch the SPI verification demo on YouTube

The demo shows:

Generate UVM → Add DUT → Adjust UVM → Update Source List → Validate → Questa Simulation

🚀 Quick Steps

🔴 1. Make Sure Python 3 Is Installed

Python 3 is required for the extension's generation engine.

Check your installation:

python --version

If Python 3 is not installed on Windows:

winget install Python.Python.3.12

Then verify:

python --version

You can also install Python from:

https://www.python.org/downloads/

If python is not available from your terminal, configure the extension's UVM Generator: Python Path setting with the path to your Python executable.

2. Generate the UVM Testbench

Open the VS Code Command Palette:

Ctrl + Shift + P

Run:

UVM: Generate Testbench

Enter your DUT/design name, then choose:

• Active — the UVM agent drives stimulus into the DUT.
• Passive — the agent observes existing activity without driving the DUT.

For a normal DUT verification flow, use Active.

3. Add Your Design / DUT

Add your existing RTL/DUT source files to your project.

This extension generates the verification environment; it does not generate or analyze your RTL/DUT.

You must provide your own DUT and connect it to the generated UVM environment.

4. Adjust the UVM for Your Design

Customize the generated UVM for your DUT/protocol as needed.

Typical files to adapt include:

• Sequence Item
• Driver
• Monitor
• Sequence
• Scoreboard
• Test
• Top/interface connections

The generated project is a reusable UVM skeleton; DUT-specific stimulus, checking, protocol behavior, and signal connections are intentionally left for the verification engineer to adapt.

5. Update the Source List

Open the Command Palette:

Ctrl + Shift + P

Run:

UVM: Update Source List

This updates src_files.list using the files that belong in the Questa compilation flow.

Make sure your DUT/RTL source files are included.

6. Validate the Testbench

Run:

Ctrl + Shift + P
→ UVM: Validate Testbench

The validator checks the generated testbench structure, source list, package/import relationships, expected components, and unresolved design-name placeholders.

A successful project reports:

Validation PASSED

7. Run Questa Simulation

Run:

Ctrl + Shift + P
→ UVM: Run Questa Simulation

This launches the generated Questa/ModelSim simulation flow using run.do.

Questa/ModelSim is required only for simulation.

Active vs Passive Agents

Active Agent

An active agent contains components that can drive the DUT:

Sequence
   ↓
Sequencer
   ↓
Driver
   ↓
DUT

Use an active agent when the UVM testbench needs to generate stimulus.

Passive Agent

A passive agent observes activity:

DUT / External Source
        ↓
      Monitor
        ↓
Scoreboard / Coverage

Use a passive agent when another source is already driving the DUT or interface.

Commands

What the Extension Generates

The generated environment uses a fixed, reusable UVM structure containing components such as:

• Interface
• Configuration
• Agent
• Driver
• Monitor
• Sequencer
• Sequence Item
• Environment
• Scoreboard
• Coverage
• SVA
• Reset Sequence
• Test
• Questa run.do
• src_files.list

The VS Code extension is the primary supported frontend.

The Python generation engine is used by the extension through its JSON CLI.

What This Extension Does — and Does Not Do

It DOES

• Generate a reusable UVM verification skeleton from a design name.
• Support active and passive agents.
• Validate generated UVM projects.
• Maintain src_files.list.
• Generate sequence items and basic sequences.
• Provide a Questa/ModelSim simulation command.
• Reuse a fixed UVM architecture and template set.

It DOES NOT

• Generate your RTL/DUT.
• Automatically understand your DUT protocol.
• Automatically create all DUT-specific driver behavior.
• Automatically create a complete DUT-specific scoreboard.
• Automatically infer arbitrary DUT port connections.
• Replace the verification engineer's protocol-specific work.

For a real project, the normal workflow is:

Existing RTL/DUT
      ↓
UVM Generator
      ↓
Generated UVM Skeleton
      ↓
Customize for Your DUT
      ↓
Update Source List
      ↓
Validate
      ↓
Questa Simulation

Project Structure

UVM_Generator_edited/
├── generator/
│   ├── generator.py       # Core generation API
│   ├── validator.py       # Lightweight structural validator
│   ├── src_list.py        # Source-list generation
│   ├── seq_item_gen.py    # Sequence-item/basic-sequence generation
│   ├── cli.py             # JSON CLI used by the VS Code extension
│   ├── templates/         # UVM template source
│   └── tests/             # Unit tests
│
├── vscode-extension/
│   └──                  # TypeScript VS Code frontend
│
└── main.py              # Legacy Tkinter wrapper

The VS Code extension is the primary supported frontend.

Development

For contributors who want to work on the project itself:

cd vscode-extension
npm install
npm run build

For the Python test suite:

python -m unittest discover -s generator/tests -t .

Contact

Ahmed Nossier

🔗 LinkedIn
📧 anossier58@gmail.com

License

MIT License