HDL support for VS Code

HDL support for VS Code with Syntax Highlighting, Snippets, Linting, Formatting and much more!

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Installation

Install it from VS Code Marketplace or Open VSX Registry.

Features

• Syntax Highlighting
  • Verilog-HDL
  • SystemVerilog
  • VHDL
  • Verilog-AMS
  • Vivado UCF constraints
  • Synopsys Design Constraints
  • Verilog Filelists (dot-F files)
  • Tcl
• Inactive Verilog/SystemVerilog preprocessor region highlighting
• VCD waveform viewer integration:
  • fliplot (build-in)
  • Vaporview (when that extension is installed)
• Simple Snippets
• Linting support from:
  • Icarus Verilog - iverilog
  • Modelsim - modelsim
  • Verilator - verilator
  • Vivado Logical Simulation - xvlog
  • Slang - slang
  • Verible Verilog Lint - verible-verilog-lint
• Ctags Integration
  • Autocomplete
  • Document Symbols Outline
  • Hover over variable declaration
  • Go to Definition & Peek Definition
  • Module Instantiation
• Language Server support from:
  • svls
  • veridian
  • HDL Checker
  • verible-verilog-ls
  • vhdl_ls
  • tclsp
• Formatting support from:
  • verilog-format
  • istyle-verilog-formatter
  • verible-verilog-format

Usage Instructions

Commands

• Rerun lint tool

  Choose a lint tool from the list and run it manually. Useful if the code was changed by an external script or version control system.

• Verilog: Doctor

  Diagnose the configured external tools and write a report to the Verilog Doctor output channel. It checks Ctags, the selected linter, formatters, WSL setup, enabled language servers, include paths, and config files without running linting or formatting on user files.

• Instantiate Module

  Choose a module present in your workspace to instantiate it in the current file.

• Open Fliplot Waveform Viewer

  Open the embedded Fliplot waveform viewer and load a VCD file.

• Verilog: Open Waveform

  Open a VCD waveform file with the configured waveform viewer. By default, this command uses Vaporview when the lramseyer.vaporview extension is installed and falls back to the embedded Fliplot viewer otherwise. Configure waveform viewer behavior under verilog.waveform.

• All linters expect the executable binary ( iverilog , verilator ...) to be present in the PATH environment variable, unless otherwise specified.

• On Windows, Vivado xvlog can be discovered when it is provided as xvlog.bat or xvlog.cmd on PATH or under verilog.linting.path.

• Set verilog.linting.linter to none to disable automatic linting without warnings.

• While using `include directives, the path to the files should be relative to the workspace directory, unlessrunAtFileLocation is enabled (not supported by all linters)

Inactive Preprocessor Regions

Inactive Verilog/SystemVerilog preprocessor branches controlled by `ifdef, `ifndef, `elsif, `else, and `endif are highlighted in the editor. The lightweight scanner uses macros defined in the current document plus any workspace-wide macros configured in verilog.preprocessor.defines.

{
    "verilog.preprocessor.defines": ["SIMULATION", "USE_VENDOR_IP"],
    "verilog.preprocessor.inactiveCode.enabled": true,
    "verilog.preprocessor.inactiveCode.opacity": 0.45,
    "verilog.preprocessor.inactiveCode.foregroundColor": "",
    "verilog.preprocessor.inactiveCode.backgroundColor": "rgba(255, 0, 0, 0.12)"
}

Leave foregroundColor or backgroundColor empty to use the theme/default styling. This feature does not resolve `include files, filelists, or simulator arguments such as +define+FOO and -D FOO.

Ctags Integration

This extension uses the tags created using Ctags to provide many of its features. It is recommended to use Universal Ctags as it supports SystemVerilog also, compared to Exuberant Ctags and other older versions. The tags are stored in memory and not as separate files.

Currently the integrated feature supports only tags in the currently opened file, not tags in other files. Enable this integration with the verilog.ctags.enabled setting. However, you can use other independent Ctags extensions to find definitions from any file.

For example Ctags Companion works well with this extension by adding the following settings on .vscode/settings.json in your workspace.

{
    "ctags-companion.command": "ctags -R --fields=+nKz --langmap=SystemVerilog:+.v -R rtl /opt/uvm-1.2/src",
}

It searches for definitions not only in the workspace, but also in files outside the workspace (ex. /opt/uvm-1.2/src in the example above). It also supports the readtags command included in Universal Ctags, allowing for fast searches from large workspaces.

Installation of Universal Ctags

• Windows - Daily builds are available at ctags-win32
• Linux - Installation instructions are here
• macOS - Install through Homebrew from here

Add the installation path of Ctags binary in your PATH environment variable or mention it in verilog.ctags.path setting.

Language Servers (Experimental)

We currently support the following Language Servers and enabled for Verilog-HDL, SystemVerilog and VHDL. You can enable multiple Language Servers at the same time. It might be pretty unstable because it's currently in the experimental support. If you encounter any problems even if it's not related to this feature, deleting all the config may solve the problem.

Install svls via cargo:

cargo install svls

Install vhdl_ls via cargo:

cargo install vhdl_ls

Tcl support is provided by tclsp for Tcl/SDC/XDC/UPF files. Configure it under verilog.languageServer.tclsp and install tclint (provides the tclsp binary). Recommended install via uv:

uv tool install tclint

Formatting (Experimental)

We currently support Verilog-HDL file formatting with the following formatters.

• verilog-format
• thomasrussellmurphy/istyle-verilog-formatter.
• verible-verilog-format

You can format the Verilog-HDL file by typing Ctrl-Shift-p, then select Format Document. Entire file formatting is supported. Selected range formatting is not supported yet. All the settings for formatting is under verilog.formatting namespace. The verilog.formatting.verilogFormat.settings path supports ${env:VAR} and ~ expansion, so values such as ${env:HOME}/.verilog-format.properties and ~/.verilog-format.properties can be used.

Guidelines for Contributing

Extension Development

Launch in Debug Mode

1. Install dependencies with npm install.
2. Open the repository in VS Code and start the default build task (watch) or simply press F5—the Launch Extension configuration in .vscode/launch.json will run the build task automatically.
3. In the Run and Debug view, pick Launch Extension and start debugging. VS Code will open an Extension Development Host pointing at the bundled language_examples workspace so you can try the features immediately.
4. Set breakpoints in the src files; the compiled output in out is mapped via sourcemaps so the breakpoints hit your TypeScript sources.

Logs

Logs are outputted to LogOutputChannel in th VS Code. You can check it by opening the Output pane in VS Code and choose Verilog in the drop-down menu.

Helpful links

• Verilog in VSCode With Linting (Using Modelsim) - YouTube
• A Productive VSCode Setup for SystemVerilog Development - Igor Freire

Thanks

• To all our Contributors
• Textmate Package for Verilog
• SublimeLinter-contrib-iverilog
• SublimeLinter-contrib-vlog
• yangsu/sublime-vhdl
• Sublime EDA
• dalance/svls
• vivekmalneedi/veridian
• suoto/hdl_checkerChecker
• chipsalliance/verible
• ericsonj/verilog-format
• thomasrussellmurphy/istyle-verilog-formatter
• slang C++ docs
• Digital-EDA/Digital-IDE: All in one vscode plugin for HDL development
  • configs/tcl.configuration.json and syntaxes/tcl.tmlanguage.json are obtained from the repo.
• eirikpre/VSCode-SystemVerilog: SystemVerilog support in VS Code
  • SystemVerilog syntax is obtained from the repo.
• raczben/fliplot: HTML & Js based VCD viewer
• wavedrom/vcd-samples: sample VCD files

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