Verilog Language Extension adds Verilog/SystemVerilog editor support to Visual Studio 2022 and later.
What it does:
- Adds syntax highlighting for Verilog/SystemVerilog source and header files.
- Supports
.v, .vh, .verilog, .sv, and .svh files.
- Provides individually configurable colors for Verilog keywords and extension-specific display items.
- Highlights line comments, block comments, static strings, macros, variables, functions, duplicate declarations, and nested bracket depth.
- Shows QuickInfo hover text for Verilog keywords, modules, declarations, variables, and missing/unknown symbols.
- Adds code outlining/folding for modules, functions, tasks, begin/end blocks, case blocks, always blocks, if/else blocks, and preprocessor conditional regions.
- Handles paste, delete, multi-change edits, and larger Verilog files with background parsing and refresh support.
- Includes a Snapshot Exporter and local snapshot-regression tooling for extension development and validation.
- Includes a Verilog Project template preview for FPGA-oriented starter projects using external tools such as WSL, yosys, nextpnr, ecppack, and board-specific programmers.
Set custom keyword colors in Tools - Options - Environment - Fonts and Colors.
Suggestions and comments welcome; see GitHub issues. Pull Requests are appreciated.
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