Adds Verilog and SystemVerilog language support to the Visual Studio editor.
What it does:
- Adds syntax highlighting for Verilog and SystemVerilog source and header files.
- Supports
.v, .vh, .verilog, .sv, and .svh files.
- Provides individually configurable colors for Verilog/SystemVerilog keywords and syntax categories.
- Highlights comments, string literals, macros, preprocessor directives, variables, functions, user-defined types, duplicate declarations, and nested bracket depth.
- Identifies inactive preprocessor regions and displays inactive code accordingly.
- Shows QuickInfo hover information for keywords, modules, declarations, variables, system tasks/functions, and unresolved symbols.
- Supports Go To Definition for recognized Verilog/SystemVerilog symbols.
- Supports Find All References for recognized Verilog/SystemVerilog symbols.
- Adds code outlining/folding for modules, functions, tasks, begin/end blocks, case blocks, always blocks, if/else blocks, and preprocessor conditional regions.
- Handles paste, delete, multi-change edits, and larger Verilog files with background parsing and refresh support.
- Includes an (experimental) Verilog Project template preview for FPGA-oriented starter projects using external tools such as WSL, Yosys, nextpnr, ecppack, and board-specific programmers.
Set custom syntax colors in Tools - Options - Environment - Fonts and Colors.
Suggestions and comments welcome; see GitHub issues. Pull Requests are appreciated.
| |
