V3S for VS2017

Please visit my homepage http://www.vide-software.at for detailed information about the VHDL/Verilog/SystemVerilog code editor V3S. V3S fully supports VHDL2008, and I am continuously working to improve Verilog/SystemVerilog support as well. Just download the extension - it will work without restrictions for a 30-day trial period.

The following list provides just an overview to the most useful and powerful features of V3S. Please refer to the full feature-list for a detailed description of all features.ÂÂ

• Refactorization, Renaming
• Library View
• Hierarchy View
• Parameter Help
• Create Testbench Wizard
• Check custom naming rules/conventions
• Quicksearch dialog
• Find all references
• Goto Declaration/Definition
• Import existing Altera/Xilinx projects
• Type-time error checking
• Smart indentation, smart copy/paste
• Record resolution
• Code completion, auto complete
• Comment/Uncomment code blocks
• Block selection
• Outlining/Code folding
• Code Statistics
• Protected Type Support
• Extended code snippets (quick component instantiation, ...)
• Tuple highlighting (braces, if-then-elsif-else-end, case-when-end, ...)
• Navigation (goto definition/declaration of components, variables, signals, ...)
• Syntax/semantic highlighting (types, signals, ports, libraries, constants, attributes, ...)
• Quickinfo/Mouse hover (number conversion bin/hex/dec, type resolution, signal type information, ...)