Verita - AI-Powered Verilog Verification

Verita is a powerful VSCode extension that brings AI-powered verification capabilities to your Verilog and SystemVerilog development workflow. Automatically generate testbenches, run simulations, and verify your RTL designs with hierarchical testing support.

Features

🚀 Automated Testbench Generation

• AI-powered testbench creation for Verilog/SystemVerilog modules
• Intelligent test case generation based on your RTL design
• Support for both combinational and sequential logic

🔍 Hierarchical Testing

• Automatically detect module dependencies
• Test modules in the correct hierarchical order
• Bottom-up verification strategy for complex designs

⚡ One-Click Verification

• Right-click any Verilog file to verify
• Integrated context menu for quick access
• Real-time verification results in the sidebar

📊 Interactive Results Panel

• View simulation results directly in VSCode
• Detailed waveform analysis
• Pass/fail indicators for each test case

🔧 Multi-File Project Support

• Automatic dependency detection
• Handle complex multi-module designs
• Support for include files and module hierarchies

Requirements

• VSCode 1.103.0 or higher
• Backend API server (configuration required)
• Icarus Verilog (iverilog) for simulation (handled by backend)

Getting Started

1. Install the extension from the VSCode Marketplace
2. Configure the backend API endpoint in settings
3. Open a Verilog/SystemVerilog file
4. Right-click and select "ChipVerify: Verify This File" or use the ChipVerify sidebar panel

Extension Settings

This extension contributes the following settings:

• chipverifyagent.apiUrl: Backend API server URL (default: configured in config.json)
• chipverifyagent.enableHierarchicalTest: Enable/disable hierarchical testing feature
• chipverifyagent.timeout: Verification timeout in seconds

Usage

Basic Verification

1. Open a .v or .sv file
2. Right-click in the editor or file explorer
3. Select "ChipVerify: Verify This File"
4. View results in the ChipVerify panel

Hierarchical Testing

1. Click the ChipVerify icon in the Activity Bar
2. Select "Hierarchical Testing" from the panel
3. Choose your top-level module file
4. The extension will automatically:
   • Detect all dependencies
   • Test modules in hierarchical order
   • Display results for each module

Command Palette Commands

• ChipVerify: Verify This File - Verify the current Verilog file
• ChipVerify: Hierarchical Testing - Start hierarchical verification
• Upload RTL & Start Verification - Manual upload and verification
• Test API Connection - Verify backend connectivity

Supported File Types

• .v - Verilog
• .sv - SystemVerilog
• .vh - Verilog header files
• .svh - SystemVerilog header files

Known Issues

• Large designs may take longer to verify depending on complexity
• Backend server must be running and accessible
• Network connectivity required for API-based verification

Release Notes

1.0.0

Initial release of Verita featuring:

• AI-powered testbench generation
• Hierarchical testing support
• Multi-file dependency detection
• Interactive results panel
• Context menu integration
• TLS/HTTPS support for secure communication

Contributing

Found a bug or have a feature request? Please file an issue on our GitHub repository.

Privacy & Security

• All verification is performed on your configured backend server
• No code is sent to third-party services without your explicit configuration
• TLS encryption supported for secure communication

Support

For questions, issues, or feature requests, please contact Future Intelligence Lab or visit our documentation.

Enjoy fast, AI-powered Verilog verification with Verita!